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參數(shù)資料
| 型號： | XC9500 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC9500 In-System Programmable CPLD Family |
| 中文描述： | XC9500在系統(tǒng)可編程CPLD系列 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 172K |
| 代理商： | XC9500 |
XC9500 In-System Programmable CPLD Family
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
3
R
Function Block
Each Function Block, as shown in
Figure 2
, is comprised of
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the Fast CONNECT switch
matrix. These 18 outputs and their corresponding output
enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Thirty-six inputs provide 72 true and com-
plement signals into the programmable AND-array to form
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
Each FB (except for the XC9536) supports local feedback
paths that allow any number of FB outputs to drive into its
own programmable AND-array without going outside the
FB. These paths are used for creating very fast counters
and state machines where all state registers are within the
same FB.
Figure 2:
XC9500 Function Block
Macrocell 18
Macrocell 1
Programmable
AND-Array
Product
Term
Allocators
From
Fast CONNECT II
Switch Matrix
DS063_02_110501
36
1
To Fast CONNECT II
Switch Matrix
To I/O Blocks
OUT
Global
Set/Reset
3
18
PTOE
18
18
Global
Clocks
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