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參數(shù)資料
| 型號： | XC9101C50AKR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 156K |
| 代理商： | XC9101C50AKR |
<Current Limiter>
The current flowing through the coil is monitored by the limiter comparator via the V
IN
and Isen pins. The limiter
comparator outputs a signal when the potential difference between the VIN and Isen pins reaches 150 mV or more.
This signal is converted to a logic signal and handled as a DFF reset signal for the internal limiter circuit. When a
reset signal is input, a signal is output immediately at the EXT pin to turn off the MOS switch. When the limiter
comparator sends a signal to enable data acceptance, a signal to turn on the MOS switch is output at the next
clock pulse. If at this time the potential difference between the V
IN
and Isen pins is great, operation is repeated to
turn off the MOS switch again. DFF operates in synchronization with the clock signal of the CLK pin.
<Soft Start>
The soft start function is made available by attaching a capacitor and resistor to the CE/SS pin. The Vref voltage
applied to the Verr amplifier is restricted by the start-up voltage of the CE/SS pin. Doing so ensures that the Verr
amplifier operates with its two inputs in balance, thereby preventing the ON-TIME signal from becoming stronger
than necessary. Consequently, soft start time needs to be set sufficiently longer than the time set to CLK. The
start-up time of the CE/SS pin equals the time set for soft start (see the section "Functional Settings" for constants).
<PWM/PFM Switching>
The controllers of the XC9102 series switch between PFM and PWM modes automatically. The PFM/PWM
comparator monitors the current each time switching occurs. When the current decreases to a certain value or
below, a shift from PWM to PFM mode occurs.
To be specific, current-limiting PFM is carried out in the PFM mode. When V
OUT
(or the FB voltage in the case of
type D) decreases below the set value, the Verr amplifier sends a signal directly to the logic block to turn on the
external MOS switch. An ON signal is output from the EXT pin in synchronization with the clock signal of the CLK
pin. When the external MOS switch is turned on, a current flows through the coil at the same time. The external
MOS switch is turned off by a current-limit signal of the limiter comparator (set to a different level than the limiter
voltage in PWM mode), the leading edge of the next clock signal, or an increase in the output voltage. The logic is
programmed for the PFM mode so that a signal is generated in synchronization with the leading edge of the clock
signal at CLK to turn off the external switch for a fixed period.
9
XC9101/02 Series
PWM Controlled, PWM//PFM Switchable Step-Up DC/DC Converters
<Mixer and PWM>
The mixer modulates the signal sent from Verr by the signal from Ierr. The modulated signal enters the PWM
comparator for comparison with the sawtooth pulses generated at the CLK pin. If the signal is greater than the
sawtooth waveforms, a signal is sent to the output circuit to turn on the external switch.
The controller stops required operation if the output voltage exceeds the set value after a single cycle of switching
operation and waits for another drop in the output voltage. If the set value is not exceeded, pulses are output
successively. Since the current flowing through the coil is limited by the limiter comparator, output voltage ripple is
held below a certain value.
If the PFM/PWM comparator indicates PWM mode constantly as a result of frequent occurrence of successive
pulses, the controller operates in PWM mode continuously. As the PWM mode is active constantly behind the PFM
mode, shifting between modes occurs smoothly. Clock pulses at the CLK pin do not stop even in PFM mode.
D
CLK
Q
/RESET
PWM/PFM switching signal
CLK sync signal
Output signal to EXT pin
Limiter signal
PWM/PFM switching signal
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