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參數(shù)資料
| 型號(hào)： | XC9101C50AKR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 156K |
| 代理商： | XC9101C50AKR |
2. Oscillation Frequency
The oscillation frequency of the internal clock generator is approximated by the following equation according to
the values of capacitor and resistor attached to the CLK pin.
Example: When Cclk = 330 pF and Rclk = 5 k
, f = 1/(-330e
-12
x 5e
3
x ln(0.2)) = 376.56 kHz.
3. Gain and Frequency Characteristics of the Verr Amplifier
The gain at output and frequency characteristics of the Verr amplifier are adjusted by the values of capacitor
and resistor attached to the CC/GAIN pin. It is generally recommended to attach a CC of 220 to 1,000 pF
without an RGAIN. The greater the CC value, the more stable the phase and the slower the transient response.
4. Current Limiting
The current limiting value is approximated by the following equation according to resistor Rsen inserted
between the V
IN
and Isen pins. Double function, current FB input and current limiting, is assigned to the Isen
pin.
Example: When Rsen = 100 m
, Ilimit = 0.15/0.1 = 1.5 A
11
Ilimit = 0.15/Rsen
f = 1/(-Cclk x Rclk x ln0.2)
XC9101/02 Series
PWM Controlled, PWM//PFM Switchable Step-Up DC/DC Converters
CLK pin
[Inside IC, XC9101/02]
Rclk
Cclk
CLK Generater
[Inside IC, XC9101/02]
Isen pin
Rsen
+
-
V
IN
pin
Limiter signal
Comparator with
150-mV offset
CC/GAIN pin
[Inside IC, XC9101/02]
RGAIN
CC
Vout/FB
+
-
Vref
Verr
RVerr
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