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參數(shù)資料
| 型號： | XC9101C50AKR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 8/21頁 |
| 文件大小： | 156K |
| 代理商： | XC9101C50AKR |
Block Diagram
Operation Description
<Ierr amplifier>
The Ierr amplifier monitors the coil current. The potential difference between the V
IN
and Isen pins are sampled
each time of switching operation. Then the potential difference is amplified or held, as necessary, and input to the
mixer. The Ierr amplifier outputs a signal ensuring that the greater the potential difference between the V
IN
and Isen
pins, the smaller the switching current. The gain and frequency characteristics of this amplifier are fixed internally.
8
<Verr amplifier>
The Verr amplifier is designed to monitor the output voltage. A fraction of the voltage applied to internal resistors
(R1, R2) in the case of a type C controller, and the voltage of the FB pin in the case of a type D controller are fed
back and compared with the reference voltage. In response to feedback of a voltage lower than the reference
voltage, the output voltage of the Verr amplifier increases.
The output of the Verr amplifier goes directly to the PFM/PWM switch logic and is also led to the mixer via a
resistor (RVerr). The former signal acts as a voltage sensor in PFM mode. The latter signal works as a pulse width
control signal in PWM mode. Connecting an external capacitor and resistor makes it possible to set the gain and
frequency characteristics of Verr amplifier signals (see the section "Functional Settings" for constants).
Step-up DC/DC converter controllers of the XC9101/9102 series carry out pulse width modulation (PWM) according
to the multiple feedback signals of the output voltage and coil current. The XC9102 series achieves high efficiency
within a wide load range, shifting to pulse frequency modulation (PFM) under a light load condition.
The internal circuits consist of different blocks that operate at V
IN
or the stabilized power (1.8 V) of the internal
regulator. The output setting voltage of type C controller and the FB pin voltage (Vref = 0.9 V) of type D controller
have been adjusted and set by laser-trimming.
With regard to clock pulses, a capacitor and resistor connected to the CLK pin generate sawtooth waveforms
whose top and bottom are 0.7 V and 0.15 V, respectively. The frequency can be set within a range of 100 to 600
kHz by external constants (see the section "Functional Settings" for constants). The clock pulses are processed to
generate a signal used for synchronizing internal sequence circuits.
<Clock>
XC9101/02 Series
PWM Controlled, PWM//PFM Switchable Step-Up DC/DC Converters
EXT
Isen
V
IN
CE/SS
V
SS
V
OUT
/FB
CC/GAIN
CLK
+
-
+
-
Sawtooth Wave,
Internal CLK
generator
Chip Enable,
Soft Start up
EXT timing
control logic
+
-
+
-
Verr
+
-
PWM
+
-
Ierr
+
-
Internal Voltage
Regulator
Current Limit
Protection
PFM/PWM
switch logic
PFM/PWM comp.
Limitter comp.
1.8V
to internal
circuit
Vref generator
CE,UVLO
to internal
circuit
0.9V
Sampling
R1
R2
RVerr
MIX
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