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參數(shù)資料
| 型號： | XC7K420T-3FFG901I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, PBGA900 |
| 封裝： | LEAD FREE, FBGA-900 |
| 文件頁數(shù)： | 44/50頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | XC7K420T-3FFG901I |
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Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
49
Table 55: Package Skew
Symbol
Description
Device
Package
Value
Units
TPKGSKEW
Package Skew(1)
XC7K70T
FBG484
ps
FBG676
ps
XC7K160T
FBG484
ps
FBG676
ps
FFG676
ps
XC7K325T
FBG676
ps
FFG676
ps
FBG900
ps
FFG900
ps
XC7K355T
FFG901
ps
XC7K410T
FBG676
ps
FFG676
ps
FBG900
ps
FFG900
ps
XC7K420T
FFG901
ps
FFG1156
ps
XC7K480T
FFG901
ps
FFG1156
ps
Notes:
1.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2.
Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Table 56: Sample Window
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
TSAMP
Sampling Error at Receiver Pins(1)
0.51
0.56
0.61
ps
TSAMP_BUFIO
Sampling Error at Receiver Pins using BUFIO(2)
0.30
0.35
0.40
ps
Notes:
1.
This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2.
This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 57: Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS/TPHCS
Setup/Hold of I/O clock
–0.20/
1.79
–0.20/
2.01
–0.20/
2.33
ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS
Clock-to-Out of I/O clock
6.29
6.98
8.02
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC7K420T-L2FF1156E | 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 1156FCBGA |
| XC7K420T-L2FF901E | 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 420K KINTEX-7 901FBGA 制造商:Xilinx 功能描述:IC FPGA 380 I/O 901FCBGA |
| XC7K420T-L2FFG1156E | 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 1156FCBGA |
| XC7K420T-L2FFG901E | 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 380 I/O 901FCBGA |
| XC7K480T-1FF1156C | 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 1156FCBGA |
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