參數(shù)資料
型號(hào)： XC7K420T-3FFG901I
廠商： XILINX INC
元件分類(lèi)： FPGA
英文描述： FPGA, PBGA900
封裝： LEAD FREE, FBGA-900
文件頁(yè)數(shù)： 4/50頁(yè)
文件大?。?/td> 1218K
代理商： XC7K420T-3FFG901I
Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
12
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Kintex-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject
to the same guidelines as the Switching Characteristics, page 15. In each table, the I/O bank type is either High
Performance (HP) or High Range (HR).
XADC Reference(4)
External Reference
VREFP
Externally supplied reference voltage
1.20
1.25
1.30
V
On-Chip Reference
Ground VREFP pin to AGND,
Tj = –40°C to 100°C
1.2375
1.25
1.2625
V
Power Requirements
Analog Power Supply
VCCADC
1.71
1.8
1.89
V
Analog Supply Current
ICCADC
Analog circuits in powered up state
–
20
mA
Notes:
1.
Offset and gain errors are removed by enabling the XADC automatic gain calibration feature.
2.
See the ADC chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.
3.
See the Timing chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.
4.
Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted. On-chip reference variation is
±1%.
Table 20: Networking Applications Interface Performances
Description
I/O Bank Type
Speed Grade
Units
-3
-2
-1
-1L
SDR LVDS transmitter
(using OSERDES; DATA_WIDTH = 4 to 8)
HR
710
625
Mb/s
HP
710
625
Mb/s
DDR LVDS transmitter
(using OSERDES; DATA_WIDTH = 4 to 10)
HR
1055
800
667
Mb/s
HP
1600
1400
1250
Mb/s
SDR LVDS receiver (SFI-4.1)(1)
HR
710
625
Mb/s
HP
710
625
Mb/s
DDR LVDS receiver (SPI-4.2)(1)
HR
1055
800
667
Mb/s
HP
1600
1400
1250
Mb/s
Notes:
1.
LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Table 19: XADC Specifications (Cont’d)
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
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相關(guān)代理商/技術(shù)參數(shù)
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XC7K420T-L2FF1156E 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 1156FCBGA
XC7K420T-L2FF901E 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 420K KINTEX-7 901FBGA 制造商:Xilinx 功能描述:IC FPGA 380 I/O 901FCBGA
XC7K420T-L2FFG1156E 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 1156FCBGA
XC7K420T-L2FFG901E 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 380 I/O 901FCBGA
XC7K480T-1FF1156C 制造商:Xilinx 功能描述:KINTEX-7 - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 1156FCBGA
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