參數(shù)資料
型號(hào)： XC6VCX240T-2FFG784I
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 42/52頁(yè)
文件大小： 0K
描述： IC FPGA VIRTEX 6 241K 784FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 18840
邏輯元件/單元數(shù)： 241152
RAM 位總計(jì)： 15335424
輸入/輸出數(shù)： 400
電源電壓： 0.95 V ~ 1.05 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
47
Virtex-6 CXT Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 58. Values are expressed in nanoseconds unless otherwise noted.
Table 58: Global Clock Input to Output Delay Without MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
TICKOF
Global Clock input and OUTFF without MMCM
XC6VCX75T
5.88
ns
XC6VCX130T
6.00
ns
XC6VCX195T
6.13
ns
XC6VCX240T
6.13
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 59: Global Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMGC
Global Clock Input and OUTFF with MMCM
XC6VCX75T
2.77
ns
XC6VCX130T
2.78
ns
XC6VCX195T
2.78
ns
XC6VCX240T
2.79
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
MMCM output jitter is already included in the timing calculation.
Table 60: Clock-Capable Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMCC
Clock-capable Clock Input and OUTFF with
MMCM
XC6VCX75T
2.63
ns
XC6VCX130T
2.65
ns
XC6VCX195T
2.65
ns
XC6VCX240T
2.65
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
MMCM output jitter is already included in the timing calculation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC6VCX75T 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-6 CXT Family Data Sheet
XC6VCX75T-1FF484C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 75K 484BGA
XC6VCX75T-1FF484I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA 240 I/O 484FCBGA
XC6VCX75T-1FF784C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA 360 I/O 784FCBGA
XC6VCX75T-1FF784I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA 360 I/O 784FCBGA
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