參數資料
型號: XC6VCX240T-2FFG784I
廠商: Xilinx Inc
文件頁數: 36/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 241K 784FFGBGA
產品培訓模塊: Virtex-6 FPGA Overview
產品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數: 18840
邏輯元件/單元數: 241152
RAM 位總計: 15335424
輸入/輸出數: 400
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 784-BBGA,FCBGA
供應商設備封裝: 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
41
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG}
CLK (AREG, BREG) to {P, CARRYOUT} output
0.89
1.02
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_{AREG, BREG}_MULT
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
using multiplier
5.49
6.31
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_{AREG, BREG}
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output not
using multiplier
2.40
2.76
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_DREG_MULT
CLK (DREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
5.38
6.18
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_CREG
CLK (CREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
2.40
2.76
ns
Maximum Frequency
FMAX
With all registers used
350
275
MHz
FMAX_PATDET
With pattern detector
350
275
MHz
FMAX_MULT_NOMREG
Two register multiply without MREG
262
227
MHz
FMAX_MULT_NOMREG_PATDET
Two register multiply without MREG with pattern
detect
241
209
MHz
FMAX_PREADD_MULT_NOADREG
Without ADREG
292
253
MHz
FMAX_PREADD_MULT_NOADREG_PATDET
Without ADREG with pattern detect
292
253
MHz
FMAX_NOPIPELINEREG
Without pipeline registers (MREG, ADREG)
196
170
MHz
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers (MREG, ADREG)
with pattern detect
184
160
MHz
Table 51: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-2
-1
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