TJ480
參數(shù)資料
型號(hào)： XC6VCX130T-1FFG484C
廠商： Xilinx Inc
文件頁數(shù)： 15/52頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 128K 484FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 10000
邏輯元件/單元數(shù)： 128000
RAM 位總計(jì)： 9732096
輸入/輸出數(shù)： 240
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 484-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
22
TJ480
480 Mb/s
–
0.1
UI
DJ480
Deterministic Jitter(2)(3)
–
0.03
UI
Notes:
1.
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX transceiver sites.
2.
Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3.
All jitter values are based on a bit-error ratio of 1e-12.
4.
PLL frequency at 1.5625 GHz and OUTDIV = 1.
5.
PLL frequency at 2.5 GHz and OUTDIV = 2.
6.
PLL frequency at 2.5 GHz and OUTDIV = 4.
Table 32: GTX Transceiver Receiver Switching Characteristics
Symbol
Description
Min
Typ
Max
Units
FGTXRX
Serial data rate
RX oversampler not enabled
0.600
–
FGTXMAX
Gb/s
RX oversampler enabled
0.480
–
0.600
Gb/s
TRXELECIDLE
TIme for RXELECIDLE to respond to loss or restoration of data
–
75
–
ns
RXOOBVDPP
OOB detect threshold peak-to-peak
60
–
150
mV
RXSST
Receiver spread-spectrum
Modulated @ 33 KHz
–5000
–
0
ppm
RXRL
Run length (CID)
Internal AC capacitor bypassed
–
512
UI
RXPPMTOL
Data/REFCLK PPM offset
tolerance
CDR 2nd-order loop disabled
–200
–
200
ppm
CDR 2nd-order loop enabled
–2000
–
2000
ppm
SJ Jitter Tolerance(2)
JT_SJ3.75
Sinusoidal Jitter(3)
3.75 Gb/s
0.44
–
UI
JT_SJ3.125
Sinusoidal Jitter(3)
3.125 Gb/s
0.45
–
UI
JT_SJ3.125L
Sinusoidal Jitter(3)
3.125 Gb/s(4)
0.45
–
UI
JT_SJ2.5
Sinusoidal Jitter(3)
2.5 Gb/s(5)
0.5
–
UI
JT_SJ1.25
Sinusoidal Jitter(3)
1.25 Gb/s(6)
0.5
–
UI
JT_SJ675
Sinusoidal Jitter(3)
675 Mb/s
0.4
–
UI
JT_SJ480
Sinusoidal Jitter(3)
480 Mb/s
0.4
–
UI
SJ Jitter Tolerance with Stressed Eye(2)
JT_TJSE3.125
Total Jitter with Stressed
3.125 Gb/s
0.70
UI
JT_SJSE3.125
Sinusoidal Jitter with
Stressed Eye(7)
3.125 Gb/s
0.1
–
UI
Notes:
1.
Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2.
All jitter values are based on a bit-error ratio of 1e–12.
3.
The frequency of the injected sinusoidal jitter is 80 MHz.
4.
PLL frequency at 1.5625 GHz and OUTDIV = 1.
5.
PLL frequency at 2.5 GHz and OUTDIV = 2.
6.
PLL frequency at 2.5 GHz and OUTDIV = 4.
7.
Composite jitter with RX equalizer enabled. DFE disabled.
Table 31: GTX Transceiver Transmitter Switching Characteristics (Cont’d)
Symbol
Description
Condition
Min
Typ
Max
Units
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