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參數(shù)資料
| 型號： | XC68307FG8V |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 16/35頁 |
| 文件大?。?/td> | 172K |
| 代理商： | XC68307FG8V |
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MOTOROLA
MC68307 TECHNICAL INFORMATION
23
.
a. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum
columns.
b. Actual value depends on clock period.
c. When AS, CSx and R/W are equally loaded (
±20%), subtract 5 ns from the values given in these columns.
d. If the asynchronous input setup time (#47) requirement is satised for DTACK, the DTACK asserted to data
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time
(#27) for the following clock cycle.
e. For power-up, the MC68307 must be held in the reset state for 128 clock cycles after CLK and VCC become
stable to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum
pulse width required to reset the controller.
55
R/W asserted to data bus impedance change
40
—
20
—
ns
56e
HALT/RESET pulse width
10
—
10
—
Clks
57
BGACK negated to AS, CSx, LDS, UDS, R/W driven
1.5
—
1.5
—
Clks
58
BR negated to AS, CSx, LDS, UDS, R/W driven
1.5
—
1.5
—
Clks
NOTES:
PRELIMINARY AC TIMING SPECIFICATIONS
(VCC = 5.0V ± 0.5V or 3.3Vdc ± 0.3V; GND = 0Vdc; TA = TL to TH) (See Figures 8–10)
Num
Characteristic
3.3V
5V
Unit
8.33 MHz
16.67 MHz
Min
Max
Min
Max
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