參數(shù)資料
型號: XC68307FG8V
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16.67 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 15/35頁
文件大小: 172K
代理商: XC68307FG8V
22
MC68307 TECHNICAL INFORMATION
MOTOROLA
PRELIMINARY AC TIMING SPECIFICATIONS
(VCC = 5.0V ± 0.5V or 3.3Vdc ± 0.3V; GND = 0Vdc; TA = TL to TH) (See Figures 8–10)
Num
Characteristic
3.3V
5V
Unit
8.33 MHz
16.67 MHz
Min
Max
Min
Max
6
Clock low to address valid
60
30
ns
7
Clock high to address, data bus high impedance (maximum)
100
50
ns
8
Clock high to address (minimum)
0
0
ns
9a
Clock high to AS, CSx, LDS, UDS asserted
3
60
3
30
ns
11b
Address valid to AS, CSx, LDS, UDS asserted (read) / AS, CSx asserted
(write)
30
15
ns
12a
Clock low to AS, CSx, LDS, UDS negated
3
60
3
30
ns
13b
AS, CSx, LDS, UDS negated to address, FC invalid
30
15
ns
14b
AS, CSx, (and LDS, UDS read) width asserted
240
120
ns
14Ab
LDS, UDS width asserted
100
50
ns
15b
AS, CSx, LDS, UDS width negated
120
60
ns
17c
AS, CSx, LDS, UDS negated to R/W invalid
30
15
ns
18a
Clock high to R/W high (read)
0
60
0
30
ns
20
Clock high to R/W low (write)
0
60
0
30
ns
20Ac
AS, CSx, asserted to R/W low (write)
20
10
ns
21b
Address valid to R/W low (write)
0
0
ns
22c
R/W low to LDS, UDS asserted (write)
60
30
ns
23
Clock low to data-out valid (write)
60
30
ns
25b
AS, CSx, LDS, UDS negated to data-out invalid (write)
30
15
ns
26b
Data-out valid to LDS,UDS asserted (write)
30
15
ns
27d
Data-in valid to clock low (setup time on read)
10
5
ns
28b
AS, CSx, LDS, UDS negated to DTACK negated (asynchronous hold)
0
220
0
110
ns
29
AS, CSx, LDS, UDS negated to data-in invalid (hold time on read)
0
0
ns
29A
AS, CSx, LDS, UDS negated to data-in high impedance
180
90
ns
30
AS, CSx, LDS, UDS negated to BR negated
0
0
ns
31
DTACK asserted to data-in valid (setup time)
100
50
ns
32
HALT and RESET input transition time
0
300
0
150
ns
33
Clock high to BG asserted
0
40
0
20
ns
34
Clock high to BG negated
0
40
0
20
ns
35
BR asserted to BG asserted
1.5
3.5
1.5
3.5
Clks
36
BR negated to BG negated
1.5
3.5
1.5
3.5
Clks
37
BGACK asserted to BG asserted
1.5
3.5
1.5
3.5
Clks
38
BG asserted to control, address, data bus high impedance (AS, CSx
negated)
100
50
ns
39
BG width negated
1.5
1.5
Clks
46
BGACK width low
1.5
1.5
Clks
47d
Asynchronous input setup time
10
5
ns
53
Data-out hold from clock high
0
0
ns
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