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參數(shù)資料
| 型號： | XC95108SERIES |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD |
| 中文描述： | 在系統(tǒng)可編程的CPLD |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 70K |
| 代理商： | XC95108SERIES |
December 4, 1998 (Version 3.0)
1
Features
7.5 ns pin-to-pin logic delays on all pins
fCNT to 125 MHz
108 macrocells with 2400 usable gates
Up to 108 user I/O pins
5 V in-system programmable (ISP)
-
Endurance of 10,000 program/erase cycles
-
Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
90 product terms drive any or all of 18 macrocells
within Function Block
-
Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP
and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
1
XC95108 In-System Programmable
CPLD
December 4, 1998 (Version 3.0)
1
1*
Product Specification
Clock Frequency (MHz)
Typical
I
CC
(mA)
0
50
100
(180)
(250)
(170)
200
300
100
High Performance
Low Power
X5898
Figure 1: Typical ICC vs. Frequency for XC95108
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