參數(shù)資料
型號： XC5VLX110T-3FFG1136C
廠商： Xilinx Inc
文件頁數(shù)： 18/91頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-5 110K 1136FBGA
產(chǎn)品變化通告： Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 LXT
LAB/CLB數(shù)： 8640
邏輯元件/單元數(shù)： 110592
RAM 位總計： 5455872
輸入/輸出數(shù)： 640
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1136-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1136-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML523-FXT-UNI-G-J-ND - BOARD EVAL FOR VIRTEX-5
HW-V5-ML523-FXT-UNI-G-ND - BOARD EVAL FOR VIRTEX-5
HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
25
CRC Block Switching Characteristics
Ethernet MAC Switching Characteristics
Consult UG194: Virtex-5 FPGA Tri-mode Ethernet Media Access Controller User Guide for further information.
Endpoint Block for PCI Express Designs Switching Characteristics
Consult UG197: Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information.
JT_SJ750
Sinusoidal Jitter(4)(6)
750 Mb/s
0.57
UI
JT_SJ150
Sinusoidal Jitter(4)(6)
150 Mb/s
0.57
UI
SJ Jitter Tolerance with Stressed Eye(3)
JT_TJSE4.25
Total Jitter with Stressed
Eye(7)
4.25 Gb/s
0.69
UI
JT_SJSE4.25
Sinusoidal Jitter with
Stressed Eye(7)
4.25 Gb/s
0.1
UI
Notes:
1.
Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3.
All jitter values are based on a Bit Error Ratio of 1e–12.
4.
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
5.
PLL frequency at 1.6 GHz and OUTDIV = 1.
6.
GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
7.
Composite jitter with RX equalizer enabled. DFE disabled.
Table 48: CRC Block Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
FCRC
CRCCLK maximum frequency
325
270
MHz
Table 49: Maximum Ethernet MAC Performance
Symbol
Description
Conditions
Speed Grade
Units
-3
-2
-1
FTEMACCLIENT
Client interface maximum frequency
10 Mb/s – 8-bit width
1.25
MHz
100 Mb/s – 8-bit width
12.5
MHz
1000 Mb/s – 8-bit width
125
MHz
2000 Mb/s – 16-bit width
125
MHz
FTEMACPHY
Physical interface maximum frequency
10 Mb/s – 4-bit width
2.5
MHz
100 Mb/s – 4-bit width
25
MHz
1000 Mb/s – 8-bit width
125
MHz
2000 Mb/s – 8-bit width
250
MHz
Table 50: Maximum Performance for PCI Express Designs
Symbol
Description
Speed Grade
Units
-3
-2
-1
FPCIECORE
Core clock maximum frequency
250
MHz
FPCIEUSER
User clock maximum frequency
250
MHz
Table 47: GTX_DUAL Tile Receiver Switching Characteristics (Cont’d)
Symbol
Description
Min
Typ
Max
Units
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