參數(shù)資料
型號(hào): XC5VLX110T-3FFG1136C
廠商: Xilinx Inc
文件頁(yè)數(shù): 14/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 110K 1136FBGA
產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LXT
LAB/CLB數(shù): 8640
邏輯元件/單元數(shù): 110592
RAM 位總計(jì): 5455872
輸入/輸出數(shù): 640
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1136-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1136-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML523-FXT-UNI-G-J-ND - BOARD EVAL FOR VIRTEX-5
HW-V5-ML523-FXT-UNI-G-ND - BOARD EVAL FOR VIRTEX-5
HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
21
Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input
voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult UG198: Virtex-5 FPGA
RocketIO GTX Transceiver User Guide for further details.
X-Ref Target - Figure 7
Figure 7: Peak-to-Peak Differential Output Voltage
Table 41: GTX_DUAL Tile Clock DC Input Level Specification(1)
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
VIDIFF
Differential peak-to-peak input voltage
210
800
2000
mV
VISE
Single-ended input voltage
105
400
1000
mV
RIN
Differential input resistance
90
105
130
Ω
CEXT
Required external AC coupling capacitor
100
nF
Notes:
1.
VMIN = 0V and VMAX = 1200mV
X-Ref Target - Figure 8
Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 9
Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
0
+V
–V
P–N
DVPPOUT
ds202_02_081809
0
+V
P
N
VISE
ds202_03_052708
0
+V
–V
P – N
VIDIFF
ds202_04_052708
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