參數(shù)資料
型號: XC5202-5PQ100C
廠商: Xilinx Inc
文件頁數(shù): 38/73頁
文件大?。?/td> 0K
描述: IC - FPGA SPEED GRADE 5 COM TEMP
產(chǎn)品變化通告: XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝: 66
系列: XC5200
LAB/CLB數(shù): 64
邏輯元件/單元數(shù): 256
輸入/輸出數(shù): 81
門數(shù): 3000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-QFP(14x20)
其它名稱: Q858790
XC5202-5PQ1000C
XC5202-5PQ1000C-ND
R
November 5, 1998 (Version 5.2)
7-125
XC5200 Series Field Programmable Gate Arrays
7
Configuration Switching Characteristics
VALID
PROGRAM
INIT
Vcc
PI
T
POR
T
ICCK
T
CCLK
T
CCLK OUTPUT or INPUT
M0, M1, M2
DONE RESPONSE
<300 ns
>300 ns
RE-PROGRAM
X1532
(Required)
I/O
Master Modes
Description
Symbol
Min
Max
Units
Power-On-Reset
TPOR
215
ms
Program Latency
TPI
670
s per CLB column
CCLK (output) Delay
period (slow)
period (fast)
TICCK
TCCLK
40
640
100
375
3000
375
s
ns
Slave and Peripheral Modes
Description
Symbol
Min
Max
Units
Power-On-Reset
TPOR
215
ms
Program Latency
TPI
670
s per CLB column
CCLK (input) Delay (required)
period (required)
TICCK
TCCLK
5
100
s
ns
Note:
At power-up, VCC must rise from 2.0 to VCC min in less than 15 ms, otherwise delay configuration using PROGRAM until
VCC is valid.
Product Obsolete or Under Obsolescence
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