- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300146 > XC5200SERIES (Xilinx, Inc.) Field Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | XC5200SERIES |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 33/73頁 |
| 文件大小： | 598K |
| 代理商： | XC5200SERIES |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
R
November 5, 1998 (Version 5.2)
7-121
XC5200 Series Field Programmable Gate Arrays
7
Notes:
1. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are high.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
and the phase of internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 36: Asynchronous Peripheral Mode Programming Switching Characteristics
Previous Byte D6
D7
D0
D1
D2
1
TCA
2
TDC
4
TWTRB
3
TCD
6
TBUSY
READY
BUSY
RS, CS0
WS, CS1
D7
WS/CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
DOUT
Write to LCA
Read Status
X6097
7
4
Description
Symbol
Min
Max
Units
Write
Effective Write time
(CSO, WS=Low; RS, CS1=High
1TCA
100
ns
DIN setup time
2
TDC
60
ns
DIN hold time
3
TCD
0ns
RDY
RDY/BUSY delay after end of
Write or Read
4TWTRB
60
ns
RDY/BUSY active after beginning
of Read
760
ns
RDY/BUSY Low output (Note 4)
6
TBUSY
2
9
CCLK
periods
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC68307FG8V | 16.67 MHz, MICROCONTROLLER, PQFP100 |
| XC912DG128PV8 | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP112 |
| XC95108SERIES | In-System Programmable CPLD |
| XC9572XL-10CSG48C | High Performance CPLD |
| XC9572XL-10CSG48I | High Performance CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC5202 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-3BG225C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-3BG352C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-3HQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-3HQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復。