參數(shù)資料
型號(hào)： XC4VLX80-10FFG1148C
廠商： Xilinx Inc
文件頁數(shù)： 51/58頁
文件大小： 0K
描述： IC FPGA VIRTEX-4 80K 1148-FBGA
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-4 LX
LAB/CLB數(shù)： 8960
邏輯元件/單元數(shù)： 80640
RAM 位總計(jì)： 3686400
輸入/輸出數(shù)： 768
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1148-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1148-FCPBGA（35x35）
其它名稱： 122-1497
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
55
09/07/06
1.16
Added 2.5V rows to VIN and VTS (Table 1, page 1). Updated value DVIN from 200 mV to
110 mV in Table 12, page 11. Updated speed grade specifications for XCV4FX devices in
Table 14. Updated jitter tolerance and VEYE in Table 25, page 17. Corrected equation for
TIDELAYTOTAL_ERR in Table 35, page 29.
10/06/06
1.17
SPEED SPECIFICATION version for this data sheet release: v1.62.
Table 1: Removed former note 3 on VIN.
Table 14: Moved XC4VFX12-11, XC4VFX20-11, XC4VFX60-11, and XC4VFX100-11
devices to Production status.
Table 15: Expanded to break out processor clock specifications into Characteristics
when APU Not Used and Characteristics when APU Used. Removed specs for
CPMFCMCLK, not available.
Table 25, Table 26: Updated RX and TX jitter data and notes.
Table 39: Modified TREGXB, TREGYB, and TCKSH timing parameters to comply with
v1.62 speed specification.
12/11/06
2.0
SPEED SPECIFICATION version for this data sheet release: v1.62.
Table 1: Modified Note (3) referring to 3.3V I/O design guidelines. Added IIN
parameters.
Table 2: Corrected recommended VTRX range to 0.25V – 2.5V. Added IIN parameters.
Table 7: Added LVDCI attributes with LVCMOS.
Table 13: Added Note (1) for SDR LVDS Interface requiring AC coupling above
622 MHz. Added DDR2 SDRAM (High-Performance SERDES Design) with reference
to XAPP721. Updated all specification values.
Pin-to-Pin Performance and Register-to-Register Performance tables (formerly Table
13 and Table 14) deleted.
Table 14: XC4VFX12 changed to Production status.
Table 15: Added APU-used max characteristics for -12 devices.
Table 24: Added values for Spread-Spectrum Clocking and footnote.
Table 26: Changed symbol for jitter parameters from TJ, RJ, and DJ to TJ, RJ, and DJ
respectively.
Table 32: Added Note (1) to refer to Timing Report for non-zero tap values. Made DLY
setup/hold parameters relative to C, not CLKDIV.
Table 34: Amended Note (1) to refer to Timing Report for non-zero tap values.
Table 35: Added Note (1) to refer to XAPP707 for details on IDELAY timing
characteristics. Changed TIDELAYRESOLUTION from 74 ps to 75 ps to match Timing
Analyzer. Modified formula for TIDELAYTOTAL_ERR to use 75 ps resolution.
Table 40: Added CLK-to-DOUT parameters for “with ECC” case. Added CLK-to-CLK
parameter.
Table 43, Table 44, Table 59: Added configuration parameter values for -12 speed
grade.
Table 45: Added FMAX for -12 speed grade.
Table 45, Table 46, Table 47: Added Note (6) stating that CLKIN values for DLL only
also apply to DLL and DFS together.
Table 46, Table 47: Replicated Note (5) from Table 45 and applied to all CLKIN with
DLL parameters.
Table 47, Table 50: Added notes to clarify boundary-frequency cases.
Table 48: Modified Note (1) to point to the architecture wizard for CLKFX output jitter.
Added Note (2) to indicate that PMCD outputs introduce no jitter.
Date
Version
Revisions
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4VLX80-10FFG1148I 功能描述:IC FPGA VIRTEX-4 LX 80K 1148FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC4VLX80-11FF1148C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 80640 CELLS 90NM 1.2V 1148FCBGA - Trays
XC4VLX80-11FF1148I 功能描述:IC FPGA VIRTEX-4LX 1148FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC4VLX80-11FFG1148C 功能描述:IC FPGA VIRTEX-4 LX 80K 1148FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC4VLX80-11FFG1148I 功能描述:IC FPGA VIRTEX-4 LX 80K 1148FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
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