參數(shù)資料
型號: XC4VLX40-10FFG1148C
廠商: Xilinx Inc
文件頁數(shù): 25/58頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-4 40K 1148-FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-4 LX
LAB/CLB數(shù): 4608
邏輯元件/單元數(shù): 41472
RAM 位總計(jì): 1769472
輸入/輸出數(shù): 640
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1148-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1148-FCPBGA(35x35)
其它名稱: 122-1491
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
31
CLB Switching Characteristics
Table 37: CLB Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
XC4VFX(2)
XC4VLX/SX
ALL DEVICES
Combinatorial Delays
TILO
4-input function: F/G inputs to X/Y outputs
0.15
0.17
0.20
ns, Max
TIF5
5-input function: F/G inputs to F5 output
0.36
0.35
0.40
0.46
ns, Max
TIF5X
5-input function: F/G inputs to X output
0.44
0.43
0.49
0.57
ns, Max
TIF6Y
FXINA or FXINB inputs to YMUX output
0.30
0.34
0.39
ns, Max
TINAFX
FXINA input to FX output via MUXFX
0.21
0.23
0.27
ns, Max
TINBFX
FXINB input to FX output via MUXFX
0.21
0.20
0.23
0.26
ns, Max
TBXX
BX input to XMUX output
0.59
0.58
0.65
0.76
ns, Max
TBYY
BY input to YMUX output
0.43
0.48
0.56
ns, Max
TBXCY
BX input to COUT output – Getting into carry chain(3)
0.60
0.59
0.66
0.78
ns, Max
TBYCY
BY input to COUT output – Getting into carry chain(3)
0.49
0.48
0.54
0.63
ns, Max
TBYP
CIN input to COUT output – Carry chain delay(3)
0.07
0.08
0.09
ns, Max
TOPCYF
F input to COUT output – Getting out from carry chain(3)
0.45
0.44
0.50
0.58
ns, Max
TOPCYG
G input to COUT output – Getting out from carry chain(3)
0.44
0.43
0.48
0.57
ns, Max
Sequential Delays
TCKO
FF Clock CLK to XQ/YQ outputs
0.28
0.31
0.36
ns, Max
TCKLO
Latch Clock CLK to XQ/YQ outputs
0.37
0.36
0.41
0.48
ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TDICK / TCKDI
BX/BY inputs
0.36
–0.09
0.36
–0.09
0.40
–0.09
0.47
–0.09
ns, Min
TCECK / TCKCE
CE input
0.58
–0.16
0.57
–0.16
0.64
–0.16
0.75
–0.16
ns, Min
TFXCK / TCKFX
FXINA/FXINB inputs
0.42
–0.14
0.41
–0.14
0.46
–0.14
0.54
–0.14
ns, Min
TSRCK / TCKSR
SR/BY inputs (synchronous)
1.04
–0.74
1.02
–0.73
1.15
–0.73
1.35
–0.73
ns, Min
TCINCK / TCKCIN
CIN Data Inputs (DI) – Getting out from carry chain(3)
0.52
–0.23
0.51
–0.23
0.57
–0.23
0.67
–0.23
ns, Min
Set/Reset
TRPW
Minimum Pulse Width, SR/BY inputs
0.54
0.53
0.59
0.70
ns, Min
TRQ
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
1.05
1.03
1.15
1.35
ns, Max
FTOG
Toggle Frequency (MHz) (for export control)
1181
1205
1205(4)
1028
MHz
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.
The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX
-12 column.
3.
These items are of interest for Carry Chain applications.
4.
XC4VFX -11 devices are 1181 MHz.
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