參數(shù)資料
型號(hào)： XC4VFX100-11FF1152I
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, 10544 CLBS, 1181 MHz, PBGA1152
封裝： FBGA-1152
文件頁(yè)數(shù)： 50/58頁(yè)
文件大?。?/td> 1863K
代理商： XC4VFX100-11FF1152I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
54
02/03/06
1.11
Revised the speed specification requirements in Switching Characteristics, page 12, with
parameter changes in Table 54 and Table 56. Added Note 7 to Table 2. Added to the IRPU
and IRPD specifications in Table 3. Changed LVCMOS18 to meet the JEDEC specification in
Table 7. Inserted notes into Table 8, Table 9, and Table 10. Corrected note 1 in Table 11. In
Table 12, revised Common Mode Input Voltage Range (VICM) typical from 800 mV to
600 mV and added a new Note 1. Also in Table 12, changed Common Mode Voltage
specification from 95mV to 950mV. Changed performance numbers in Table 23. Removed
the typical specification for TDJ from Table 26. Added note 2 to Table 27. In Table 35, added
maximum to TIDELAYCTRLCO_RDY, and a new parameter TIDELAYPAT_JIT. Revised Note 1 in
Table 43. Added note 5 to Table 45. Revised notes 3 and 5 in Table 50. Changed the
CLKIN_FREQ_PMCD_CLKA_MAX -12 specification in Table 53. Changed the
TBUFIO_MAX_FREQ specification in Table 59. Changed the information in the Production
03/22/06
1.12
Modified second paragraph in Power-On Power Supply Requirements. Added/Changed
numbers for ICCINTMIN, ICCAUXMIN, and ICCOMIN, and added Note 2 (Table 5). Changed the
typ value of the DC Parameter, Common Mode Input Voltage Range from 600 MV to
800 MV in Table 12. Added three DC parameters to Table 12, Input Common-Mode Voltage
(VICMC), Peak-to-Peak Differential Input Voltage (VIDIFF), and Differential Input Resistance
(RIN). Changed the SPI4.2 entry for -11 from 900 Mb/s to 1 Gb/s in Table 13. Added Note 3
to Table 15. Reduced the maximum frequency from 322 MHz to 250 MHz (in Table 25 and
Table 26). Added Note 5 to Table 40.
06/01/06
1.13
Changed VIN and VTS values and added notes to Table 1, page 1. Removed -11X speed
grade from Table 14. Updated to speed specification v1.60. Removed -11X speed grade,
changed the -12 and -11 speed grade to 6.5 Gb/s, and deleted Note 1 in Table 23, page 16.
Deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Reference
Clock total jitter, peak-peak (TGJTT) in Table 24, page 16. Changed the max value for Serial
data rate FGTX to 6.5 Gb/s. Deleted first condition and changed second condition to
2.5 Gb/s to 6.5 Gb/s for Serial data output deterministic jitter (TDJ) and deleted first
condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Serial data output
random jitter (TRJ), both in Table 26, page 18.
06/23/06
1.14.1
Virtex-4 FPGA Electrical Characteristics, page 1: removed paragraph on that introduced
the -11x for XC4VFX devices. Table 3, page 3: added new values for ICCAUXRX, ICCAUXTX,
ICCCAUXMGT, ITTX, ITRX, and new notes 2 and 3. Table 4, page 4: added new symbols and
for values ICCAUXRX, ICCAUXTX, ITTX , ITRX,IAUMGT and new notes 4 and 5. Table 12,
page 11: changed DC parameters and values and added note. Table 14: changed speed
designations for the XC4VFX devices. Table 24, page 16 and Table 25, page 17, for most
characteristics: changed conditions, speed grade (typ and max) values, and units. Table 26,
page 18, for most characteristics: changed conditions, speed grade (typ and max) values,
and units. Updated notes. Table 43, page 36: removed the Tcnfig symbol, values, and note
1. Note 2 is now Note 1, and the reference has also been changed. Table 50, page 42:
removed Input Signal Requirements. Table 54, page 44, Table 55, page 45, Table 56,
page 46, Table 57, page 47, and Table 58, page 48: corrected large speed numbers to N/A.
08/23/06
1.15
Table 24, page 16: changed value for Reference Clock Rise/Fall Time (TRCLK; TFCLK) from
65 ps Typ to 400 ps Max. Table 35, page 29: changed the speeds specification for the -12,
-11, and -10 Speed Grades for TIDELAYRESOLUTION, deleted row for
TIDELAYRESOLUTION_ERR and added row for TIDELAYTOTAL_ERR. Table 39, page 32: changed
the speeds specification for -12 Speed Grades, Sequential Delay characteristics: TREG,
TREGXB, TREGYB, TCKSH, and TREGF5. Table 65, page 52: added stepping information for
Virtex-4 FX devices.
Date
Version
Revisions
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4VFX100-11FF1517C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1517FCBGA - Trays
XC4VFX100-11FF1517CES4 制造商:Xilinx 功能描述:
XC4VFX100-11FF1517CES4S 制造商:Xilinx 功能描述:
XC4VFX100-11FF1517I 功能描述:IC FPGA VIRTEX-4FX 1517FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 FX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC4VFX100-11FF1517IES4 制造商:Xilinx 功能描述:
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