參數資料
型號： XC4VFX100-10FFG1517I
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, 10544 CLBS, 1028 MHz, PBGA1517
封裝： LEAD FREE, FBGA-1517
文件頁數： 53/58頁
文件大小： 1863K
代理商： XC4VFX100-10FFG1517I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
57
09/28/07
3.0
SPEED SPECIFICATION version for this data sheet release: v1.67.
Promoted data sheet to Production status.
Table 14: Moved XC4VFX140, all speed grades, from Advance to Production status.
Table 59: Added/updated all Global Clock Tree Skew values. Qualified Note (2) by
adding “vertical”.
Table 60: Added Package Skew values for XC4VFX40, XC4VFX100, and XC4VFX140.
Table 63: Added JTAG ID code for XC4VFX140.
12/11/07
3.1
SPEED SPECIFICATION version for this data sheet release: v1.68.
Added new copyright notice and legal disclaimer section.
Table 13: Removed table note references to XAPP700, XAPP704, and XAPP705
(obsolete). Renumbered table notes.
Table 15: Added new Note 1, renumbered subsequent table notes.
Table 30: Removed table rows for LVPECL_33, LVDS_33, and LVDSEXT_33.
Table 30, Table 31: Corrected “electron-coupled” to “emitter-coupled”.
Table 31: For LVDS Extended Mode 2.5V, corrected I/O Standard Attribute to
LVDSEXT_25.
Table 37: Added Note 4 specifying FTOG for -11 FX devices as 1181 MHz.
Table 43: Added parameter FMAX_READBACK.
Table 58: Corrected TPSFD for XC4VFX100 devices to 1.99 ns.
Section Production Stepping, page 51: Advised that current stepping level is reported
by the ISE tool in the PAR report.
04/10/08
3.2
SPEED SPECIFICATION version for this data sheet release: v1.68.
Table 28, page 22: Re-inserted table.
Table 43, page 36: Updated Symbol names for the DRP entries.
Table 63, page 51: Revised code for XC4VFX40 package to 0.
06/06/08
3.3
SPEED SPECIFICATION version for this data sheet release: v1.68.
Table 3, page 3: In Note (2), clarified differences between settings for typical and
maximum ICC numbers.
Table 24, page 16: Revised FGCLK to show different maximum frequencies depending
on the speed grade. Removed TPHASE.
Table 35, page 29: Reorganized according to IDELAYCTRL and IDELAY.
11/26/08
3.4
Table 35, page 29: Added FMAX.
06/16/09
3.5
Table 40, page 33: Changed TRCKO_DOA to a Max parameter.
08/13/09
3.6
Table 3, page 3: Updated Note 1.
Table 45, page 38: Added Note 6 reference to and updated descriptions of
CLKIN_FREQ_DLL_HF_MS_MIN and CLKIN_FREQ_FX_HF_MS_MAX.
09/09/09
3.7
Table 7, page 8: Added “LVCMOS” to Notes 3 and 4.
Date
Version
Revisions
相關PDF資料
PDF描述
XC4VFX100-11FFG1152I FPGA, 10544 CLBS, 1181 MHz, PBGA1152
XC4VFX100-11FFG1517I FPGA, 10544 CLBS, 1181 MHz, PBGA1517
XC4VFX100-12FFG1152C FPGA, 10544 CLBS, 1181 MHz, PBGA1152
XC4VFX100-12FFG1517C FPGA, 10544 CLBS, 1181 MHz, PBGA1517
XC5206-3PCG84I FPGA, 196 CLBS, 6000 GATES, 83 MHz, PQCC84
相關代理商/技術參數
參數描述
XC4VFX100-11FF1152C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1152FCBGA - Trays
XC4VFX100-11FF1152CES1 制造商:Xilinx 功能描述:
XC4VFX100-11FF1152CES4 制造商:Xilinx 功能描述:
XC4VFX100-11FF1152CES4S 制造商:Xilinx 功能描述:
XC4VFX100-11FF1152I 功能描述:IC FPGA VIRTEX-4FX 1517FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Virtex®-4 FX 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數:100 邏輯元件/單元數:238 RAM 位總計:3200 輸入/輸出數:80 門數:3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
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