參數資料
| 型號： | XC4013XL-1PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 2/16頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA C-TEMP 3.3V 1SPD 208PQFP |
| 產品變化通告： | Product Discontinuation 27/Apr/2010 |
| 標準包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數： | 576 |
| 邏輯元件/單元數： | 1368 |
| RAM 位總計： | 18432 |
| 輸入/輸出數： | 160 |
| 門數： | 13000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-82
DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
XC4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted
Global Low Skew Clock, Set-Up and Hold
Speed Grade
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Input Setup and Hold Times
No Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
TPSN/TPHN XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
2.5 / 1.5
1.2 / 2.6
1.2 / 3.0
1.2 / 3.2
1.2 / 3.7
1.2 / 4.4
1.2 / 5.5
1.2 / 5.8
1.2 / 7.1
1.2 / 7.0
1.2 / 9.4
2.2 / 1.3
1.1 / 2.2
1.1 / 2.6
1.1 / 2.8
1.1 / 3.2
1.1 / 3.8
1.1 / 4.8
1.1 / 5.0
1.1 / 6.2
1.1 / 6.1
1.1 / 8.2
1.9 / 1.2
0.9 / 2.0
0.9 / 2.3
0.9 / 2.4
0.9 / 2.8
0.9 / 3.3
0.9 / 4.1
0.9 / 4.4
0.9 / 5.4
0.9 / 5.3
0.9 / 7.1
1.7 / 1.0
0.8 / 1.7
0.8 / 2.0
0.8 / 2.1
0.8 / 2.4
0.8 / 2.9
0.8 / 3.6
0.8 / 3.8
0.8 / 4.7
0.8 / 4.6
0.8 / 6.2
0.8 / 2.1
0.8 / 3.6
0.8 / 4.6
ns
Partial Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
TPSP/TPHP
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
8.4 / 0.0
10. 5 / 0.0
11.1 / 0.0
6.1 / 1.0
11.9 / 1.0
12.3 / 1.0
6.4 / 1.0
13.1 / 1.0
11.9 / 1.0
6.7 / 1.2
12.9 / 1.2
7.3 / 0.0
9.1 / 0.0
9.7 / 0.0
5.3 / 1.0
10.3 / 1.0
10.7 / 1.0
5.6 / 1.0
11.4 / 1.0
10.3 / 1.0
5.8 / 1.2
11.2 / 1.2
6.3 / 0.0
7.9 / 0.0
8.4 / 0.0
4.6 / 1.0
9.0 / 1.0
9.3 / 1.0
4.8 / 1.0
9.9 / 1.0
9.0 / 1.0
5.1 / 1.2
9.8 / 1.2
5.5 / 0.0
6.9 / 0.0
7.3 / 0.0
4.0 / 1.0
7.8 / 1.0
8.1 / 1.0
4.2 / 1.0
8.6 / 1.0
7.8 / 1.0
4.4 / 1.2
8.5 / 1.2
3.7 / 0.5
4.0/ 0.8
4.2/ 1.0
ns
Full Delay
Global Low Skew Clock and IFF
TPSD/TPHD XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
6.8 / 0.0
8.8 / 0.0
9.0 / 0.0
6.4 / 0.0
8.8 / 0.0
9.3 / 0.0
6.6 / 0.0
10.6 / 0.0
11.2 / 0.0
6.8 / 0.0
12.7 / 0.0
6.0 / 0.0
7.6 / 0.0
7.8 / 0.0
6.0 / 0.0
7.6 / 0.0
8.1 / 0.0
6.2 / 0.0
9.2 / 0.0
9.7 / 0.0
6.4 / 0.0
11.0 / 0.0
5.2 / 0.0
6.6 / 0.0
6.8 / 0.0
5.6 / 0.0
6.6 / 0.0
7.0 / 0.0
5.8 / 0.0
8.0 / 0.0
8.4 / 0.0
6.0 / 0.0
9.6 / 0.0
4.5 / 0.0
5.6 / 0.0
5.8 / 0.0
4.8 / 0.0
6.2 / 0.0
6.4 / 0.0
5.3 / 0.0
6.8 / 0.0
7.0 / 0.0
5.5 / 0.0
8.4 / 0.0
4.8 / 0.0
5.3 / 0.0
5.5 / 0.0
ns
IFF = Input Flip-Flop or Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes:
Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XC4013XL-1PQ208C-0630 | 制造商:Xilinx 功能描述: |
| XC4013XL-1PQ208C0907 | 制造商:Xilinx 功能描述: |
| XC4013XL-1PQ208I | 功能描述:IC FPGA I-TEMP 3.3V 1SPD 208PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數:25475 邏輯元件/單元數:326080 RAM 位總計:16404480 輸入/輸出數:350 門數:- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，FCBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4013XL-1PQ208M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013XL1PQ240C | 制造商:XILINX 功能描述:* |
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