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參數(shù)資料
| 型號： | XC4003E-4VQ100I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 53/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 5V 4SPD 100-VQFP |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標準包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計： | 3200 |
| 輸入/輸出數(shù)： | 77 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 100-TQFP |
| 供應商設(shè)備封裝： | 100-VQFP（14x14） |
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R
May 14, 1999 (Version 1.6)
6-61
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overows the lead device—on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In the bitstream generation software, the user can specify
Fast CongRate, which, starting several bits into the rst
frame, increases the CCLK frequency by a factor of eight.
For actual timing values please refer to “Conguration
Switching Characteristics” on page 68. Be sure that the
serial PROM and slaves are fast enough to support this
data rate. XC2000, XC3000/A, and XC3100A devices do
not support the Fast CongRate option.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is congured as user-I/O, but LDC is then
restricted to be a permanently High user output after con-
guration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
Figure 51 on page 60 shows a full master/slave system.
The leftmost device is in Master Serial mode.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1, M0).
Figure 53: Master Serial Mode Programming Switching Characteristics
Description
Symbol
Min
Max
Units
CCLK
DIN setup
1
TDSCK
20
ns
DIN hold
2
TCKDS
0ns
Notes:
1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1
TDSCK
2
TCKDS
n
n + 1
n + 2
n – 3
n – 2
n – 1
n
X3223
Product Obsolete or Under Obsolescence
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