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參數(shù)資料
| 型號： | XC4003E-4PG120I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 66/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 5V 4-SPD 120-CPGA |
| 產品變化通告： | XC4000(E,L) Discontinuation 01/April/2002 |
| 標準包裝： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計： | 3200 |
| 輸入/輸出數(shù)： | 80 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 120-BCBGA |
| 供應商設備封裝： | 120-CPGA（34.55x34.55） |
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R
May 14, 1999 (Version 1.6)
6-11
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Set/Reset
An asynchronous storage element input (SR) can be con-
gured as either set or reset. This conguration option
determines the state in which each ip-op becomes oper-
ational after conguration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three
set/reset functions for any single ip-op are controlled by
the same conguration data bit.
The set/reset state can be independently specied for each
ip-op. This input can also be independently disabled for
either ip-op.
The set/reset state is specied by using the INIT attribute,
or by placing the appropriate set or reset ip-op library
symbol.
SR is active High. It is not invertible within the CLB.
Global Set/Reset
A separate Global Set/Reset line (not shown in Figure 1)
sets or clears each storage element during power-up,
re-conguration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.
Each ip-op is congured as either globally set or reset in
the same way that the local set/reset (SR) is specied.
Therefore, if a ip-op is set by SR, it is also set by GSR.
Similarly, a reset ip-op is reset by both SR and GSR.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See Figure 2.) A spe-
cic pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program-
mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Set/Reset sig-
nal.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is driven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) block input. The ip-ops or latches drive
the XQ and YQ CLB outputs.
Two fast feed-through paths are available, as shown in
Figure 1. A two-to-one multiplexer on each of the XQ and
YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used by
the automated router to repower internal signals.
Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4
in Figure 1) into the four internal control signals (H1,
DIN/H2, SR/H0, and EC). Any of these inputs can drive any
of the four internal control signals.
When the logic function is enabled, the four inputs are:
EC — Enable Clock
SR/H0 — Asynchronous Set/Reset or H function
generator Input 0
DIN/H2 — Direct In or H function generator Input 2
H1 — H function generator Input 1.
When the memory function is enabled, the four inputs are:
EC — Enable Clock
WE — Write Enable
D0 — Data Input to F and/or G function generator
D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
Using FPGA Flip-Flops and Latches
The abundance of ip-ops in the XC4000 Series invites
pipelined designs. This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline ip-ops. This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB ip-op, place the appropriate library
symbol. For example, FDCE is a D-type ip-op with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000X only) is called LDCE.
In XC4000 Series devices, the ip ops can be used as reg-
isters or shift registers without blocking the function gener-
ators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
The CLB setup time is specied between the function gen-
erator inputs and the clock input K. Therefore, the specied
CLB ip-op setup time includes the delay through the
function generator.
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive
(similar
to
the
XC4000/A/H
families),
edge-triggered, and dual-port edge-triggered. Depending
on the selected mode, a single CLB can be congured as
either a 16x2, 32x1, or 16x1 bit array.
PAD
IBUF
GSR
GTS
CLK DONEIN
Q1Q4
Q2
Q3
STARTUP
X5260
Figure 2: Schematic Symbols for Global Set/Reset
Product Obsolete or Under Obsolescence
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| XC4003E-4PQ100C | 功能描述:IC FPGA 100 CLB'S 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
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