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| 型號(hào)： | XC4003E-4PG120I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 5V 4-SPD 120-CPGA |
| 產(chǎn)品變化通告： | XC4000(E,L) Discontinuation 01/April/2002 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計(jì)： | 3200 |
| 輸入/輸出數(shù)： | 80 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 120-BCBGA |
| 供應(yīng)商設(shè)備封裝： | 120-CPGA（34.55x34.55） |
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R
May 14, 1999 (Version 1.6)
6-27
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Wide Edge Decoders
Dedicated decoder circuitry boosts the performance of
wide decoding functions. When the address or data eld is
wider than the function generator inputs, FPGAs need
multi-level decoding and are thus slower than PALs.
XC4000 Series CLBs have nine inputs. Any decoder of up
to nine inputs is, therefore, compact and fast. However,
there is also a need for much wider decoders, especially for
address decoding in large microprocessor systems.
An XC4000 Series FPGA has four programmable decoders
located on each edge of the device. The inputs to each
decoder are any of the IOB I1 signals on that edge plus one
local interconnect per CLB row or column. Each row or col-
umn of CLBs provides up to three variables or their compli-
ments., as shown in Figure 23. Each decoder generates a
High output (resistor pull-up) when the AND condition of
the selected inputs, or their complements, is true. This is
analogous to a product term in typical PAL devices.
Each of these wired-AND gates is capable of accepting up
to 42 inputs on the XC4005E and 72 on the XC4013E.
There are up to 96 inputs for each decoder on the
XC4028X and 132 on the XC4052X.
The decoders may
also be split in two when a larger number of narrower
decoders are required, for a maximum of 32 decoders per
device.
The decoder outputs can drive CLB inputs, so they can be
combined with other logic to form a PAL-like AND/OR struc-
ture. The decoder outputs can also be routed directly to the
chip outputs. For fastest speed, the output should be on the
same chip edge as the decoder. Very large PALs can be
emulated by ORing the decoder outputs in a CLB. This
decoding feature covers what has long been considered a
weakness of older FPGAs. Users often resorted to external
PALs for simple but fast decoding functions. Now, the dedi-
cated decoders in the XC4000 Series device can imple-
ment these functions fast and efciently.
To use the wide edge decoders, place one or more of the
WAND library symbols (WAND1, WAND4, WAND8,
WAND16). Attach a DECODE attribute or property to each
WAND symbol. Tie the outputs together and attach a PUL-
LUP symbol. Location attributes or properties such as L
(left edge) or TR (right half of top edge) should also be used
to ensure the correct placement of the decoder inputs.
On-Chip Oscillator
XC4000 Series devices include an internal oscillator. This
oscillator is used to clock the power-on time-out, for cong-
uration memory clearing, and as the source of CCLK in
Master conguration modes. The oscillator runs at a nomi-
nal 8 MHz frequency that varies with process, Vcc, and
temperature. The output frequency falls between 4 and 10
MHz.
D
N
D
C
D
B
D
A
AB
C
N
Z = D
A
A + D
B
B + D
C
C + D
N
N
~100 k
"Weak Keeper"
X6466
BUFT
Figure 22: 3-State Buffers Implement a Multiplexer
IOB
B
A
INTERCONNECT
(
C) .....
(A B C) .....
.I1
X2627
C
Figure 23: XC4000 Series Edge Decoding Example
F16K
F500K
F8M
F490
F15
X6703
OSC4
Figure 24: XC4000 Series Oscillator Symbol
Product Obsolete or Under Obsolescence
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| XC4003E-4PG120C | IC FPGA C-TEMP 5V 4-SPD 120-CPGA |
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| ASC15DTEI | CONN EDGECARD 30POS .100 EYELET |
| AMC15DTEI | CONN EDGECARD 30POS .100 EYELET |
| ASC65DRTN-S13 | CONN EDGECARD 130POS .100 EXTEND |
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| XC4003E-4PQ100C | 功能描述:IC FPGA 100 CLB'S 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4003E-4PQ100I | 功能描述:IC FPGA I-TEMP 5V 4-SPD 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4003E-4VQ100C | 功能描述:IC FPGA C-TEMP 5V 4SPD 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
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| XC4003H | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
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