參數(shù)資料
型號(hào)： XC4003E-4PG120I
廠商： Xilinx Inc
文件頁數(shù)： 25/68頁
文件大小： 0K
描述： IC FPGA I-TEMP 5V 4-SPD 120-CPGA
產(chǎn)品變化通告： XC4000(E,L) Discontinuation 01/April/2002
標(biāo)準(zhǔn)包裝： 24
系列： XC4000E/X
LAB/CLB數(shù)： 100
邏輯元件/單元數(shù)： 238
RAM 位總計(jì)： 3200
輸入/輸出數(shù)： 80
門數(shù)： 3000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 120-BCBGA
供應(yīng)商設(shè)備封裝： 120-CPGA（34.55x34.55）
R
May 14, 1999 (Version 1.6)
6-35
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
IOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and dou-
ble-length lines, quads, and longlines within the CLB array.
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Global Nets and Buffers
Both the XC4000E and the XC4000X have dedicated glo-
bal networks. These networks are designed to distribute
clocks and other high fanout control signals throughout the
devices with minimal skew. The global buffers are
described in detail in the following sections. The text
descriptions and diagrams are summarized in Table 15.
The table shows which CLB and IOB clock pins can be
sourced by which global buffers.
In both XC4000E and XC4000X devices, placement of a
library symbol called BUFG results in the software choos-
ing the appropriate clock buffer, based on the timing
requirements of the design. The detailed information in
these sections is included only for reference.
Global Nets and Buffers (XC4000E only)
Four vertical longlines in each CLB column are driven
exclusively by special global buffers.
These longlines are
in addition to the vertical longlines used for standard inter-
connect. The four global lines can be driven by either of two
types of global buffers. The clock pins of every CLB and
IOB can also be sourced from local interconnect.
Two different types of clock buffers are available in the
XC4000E:
Primary Global Buffers (BUFGP)
Secondary Global Buffers (BUFGS)
Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater exibility when used
to drive non-clock CLB inputs.
The Primary Global buffers must be driven by the
semi-dedicated pads. The Secondary Global buffers can
be sourced by either semi-dedicated pads or internal nets.
Each CLB column has four dedicated vertical Global lines.
Each of these lines can be accessed by one particular Pri-
mary Global buffer, or by any of the Secondary Global buff-
ers, as shown in Figure 34. Each corner of the device has
one Primary buffer and one Secondary buffer.
IOBs along the left and right edges have four vertical global
longlines. Top and bottom IOBs can be clocked from the
global lines in the adjacent CLB column.
A global buffer should be specied for all timing-sensitive
global signal distribution. To use a global buffer, place a
BUFGP (primary buffer), BUFGS (secondary buffer), or
BUFG (either primary or secondary buffer) element in a
schematic or in HDL code.
If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=L attribute or property
to a BUFGS symbol to direct that a buffer be placed in one
of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
L = Left, R = Right, T = Top, B = Bottom
Table 15: Clock Pin Access
XC4000E
XC4000X
Local
Inter-
connect
BUFGP
BUFGS
BUFGLS
L & R
BUFGE
T & B
BUFGE
All CLBs in Quadrant
√√√√√
√
All CLBs in Device
√√√
√
IOBs on Adjacent Vertical
Half Edge
√√√√√
√
IOBs on Adjacent Vertical
Full Edge
√√√√
√
IOBs on Adjacent Horizontal
Half Edge (Direct)
√
IOBs on Adjacent Horizontal
Half Edge (through CLB globals)
√√√√√
√
IOBs on Adjacent Horizontal
Full Edge (through CLB globals)
√√√
√
Product Obsolete or Under Obsolescence
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