- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4280 > XC3S500E-4FTG256I (Xilinx Inc)IC FPGA SPARTAN-3E 500K 256FTBGA PDF資料下載
參數(shù)資料
| 型號： | XC3S500E-4FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 101/227頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 500K 256FTBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 1164 |
| 邏輯元件/單元數(shù)： | 10476 |
| RAM 位總計： | 368640 |
| 輸入/輸出數(shù)： | 190 |
| 門數(shù)： | 500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 配用： | 122-1536-ND - KIT STARTER SPARTAN-3E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁當(dāng)前第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁
Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
19
IOBs Organized into Banks
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in Figure 13. Each bank maintains
separate VCCO and VREF supplies. The separate supplies
allow each bank to independently set VCCO. Similarly, the
When working with Spartan-3E devices, most of the
differential I/O standards are compatible and can be
combined within any given bank. Each bank can support
any two of the following differential standards: LVDS_25
outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As
an example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential
termination are a valid combination. A combination not
allowed is a single bank with LVDS_25 outputs, RSDS_25
outputs, and MINI_LVDS_25 outputs.
I/O Banking Rules
When assigning I/Os to banks, these VCCO rules must be
followed:
1.
All VCCO pins on the FPGA must be connected even if a
bank is unused.
2.
All VCCO lines associated within a bank must be set to
the same voltage level.
3.
The VCCO levels used by all standards assigned to the
I/Os of any given bank must agree. The Xilinx
development software checks for this. Table 6 and
Table 7 describe how different standards use the VCCO
supply.
4.
If a bank does not have any VCCO requirements,
connect VCCO to an available voltage, such as 2.5V or
3.3V. Some configuration modes might place additional
information.
If any of the standards assigned to the Inputs of the bank
use VREF, then the following additional rules must be
observed:
1.
All VREF pins must be connected within a bank.
2.
All VREF lines associated with the bank must be set to
the same voltage level.
3.
The VREF levels used by all standards assigned to the
Inputs of the bank must agree. The Xilinx development
software checks for this. Table 6 describes how different
standards use the VREF supply.
If VREF is not required to bias the input switching thresholds,
all associated VREF pins within the bank can be used as
user I/Os or input pins.
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in
Module 4, Pinout Descriptions. In some cases, there are
subtle differences between devices available in the same
footprint. These differences are outlined for each package,
such as pins that are unconnected on one device but
connected on another in the same package or pins that are
dedicated inputs on one package but full I/O on another.
When designing the printed circuit board (PCB), plan for
potential future upgrades and package migration.
The Spartan-3E family is not pin-compatible with any
previous Xilinx FPGA family.
Dedicated Inputs
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP, for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
exception for differential inputs (IP_Lxxx_x). For the
differential Dedicated Inputs, the on-chip differential
termination is not available. To replace the on-chip
differential termination, choose a differential pair that
supports outputs (IO_Lxxx_x) or use an external 100
Ω
termination resistor on the board.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: one diode
extends P-to-N from the pad to VCCO and a second diode
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes
limits the ability of Spartan-3E I/Os to tolerate high signal
Module 3, DC and Switching Characteristics specifies the
voltage range that I/Os can tolerate.
X-Ref Target - Figure 13
Figure 13: Spartan-3E I/O Banks (top view)
DS312-2_26_021205
Bank 0
Bank 2
Bank
3
Bank
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC2S200E-6PQ208I | IC FPGA 1.8V 1176 CLB'S 208-PQFP |
| 5205817-1 | CONN SCREWLOCK FEMALE 2 SETS/BAG |
| XC6SLX25-N3FTG256C | IC FPGA SPARTAN-6 256FBGA |
| XC2V40-5CSG144C | IC FPGA VIRTEX-II 40K 144-CSBGA |
| 5745563-1 | CONN D-SUB FEMALE SCREW LOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S500E-4PQ208C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 500K GATES 10476 CELLS 572MHZ 90NM 1.2V 208P - Trays |
| XC3S500E-4PQ208CES | 制造商:Xilinx 功能描述: |
| XC3S500E-4PQ208I | 功能描述:IC FPGA SPARTAN 3E 208PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S500E-4PQG208C | 功能描述:IC SPARTAN-3E FPGA 500K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC3S500E-4PQG208I | 功能描述:IC FPGA SPARTAN-3E 500K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。