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參數(shù)資料
| 型號(hào)： | XC3S250E-5TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 40/227頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3E 250K 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 612 |
| 邏輯元件/單元數(shù)： | 5508 |
| RAM 位總計(jì)： | 221184 |
| 輸入/輸出數(shù)： | 108 |
| 門數(shù)： | 250000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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Spartan-3E FPGA Family: DC and Switching Characteristics
DS312 (v4.1) July 19, 2013
Product Specification
134
Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
guidelines. For each device/package combination, Table 96
provides the number of equivalent VCCO/GND pairs. The
equivalent number of pairs is based on characterization and
might not match the physical number of pairs. For each
output signal standard and drive strength, Table 97
recommends the maximum number of SSOs, switching in
the same direction, allowed per VCCO/GND pair within an
I/O bank. The guidelines in Table 97 are categorized by
package style. Multiply the appropriate numbers from
SSOs allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ,
TQ, PQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. The
results for chip-scale packaging (CP132) are better than
quad-flat packaging but not as high as for ball grid array
packaging. Ball grid array packages are recommended for
applications with a large number of simultaneously
switching outputs.
Table 96: Equivalent VCCO/GND Pairs per Bank
Device
Package Style (including Pb-free)
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
XC3S100E
2
-
XC3S250E
2
3
4
-
XC3S500E
2
-
345
-
XC3S1200E
-
4
5
6
-
XC3S1600E
-
-5
6
7
相關(guān)PDF資料 |
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| 34VL02T/ST | IC EEPROM 2KBIT 400KHZ 8TSSOP |
| XC3S250E-5CPG132C | IC FPGA SPARTAN-3E 250K 132CSBGA |
| 34VL02T/MS | IC EEPROM 2KBIT 400KHZ 8MSOP |
| XC3S250E-4TQG144I | IC FPGA SPARTAN-3E 250K 144-TQFP |
| 34VL02T/MNY | IC EEPROM 2KBIT 400KHZ 8TDFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S250E-5TQG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S250E-5VQ100C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 250K GATES 5508 CELLS 657MHZ 90NM 1.2V 100VT - Trays |
| XC3S250E-5VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S250E-5VQG100C | 功能描述:IC FPGA SPARTAN-3E 250K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S250E-5VQG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
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