Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
80
Voltage Compatibility
Available SPI Flash PROMs use a single 3.3V supply
voltage. All of the FPGA’s SPI Flash interface signals are
within I/O Bank 2. Consequently, the FPGA’s VCCO_2
supply voltage must also be 3.3V to match the SPI Flash
PROM.
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
for its three power supplies
— VCCINT, VCCAUX, and VCCO
to I/O Bank 2 (VCCO_2)
— to reach their respective
power-on thresholds before beginning the configuration
process.
The SPI Flash PROM is powered by the same voltage
supply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their VCC supply reaches its minimum data
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 s as shown in
Table 56. For other vendors, this delay is as much as 20 ms.
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other VCCINT and
VCCAUX supplies, and consequently, there is no issue.
However, if the 3.3V supply feeding the FPGA's VCCO_2
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
If the FPGA's VCCINT and VCCAUX supplies are already
valid, then the FPGA waits for VCCO_2 to reach its
minimum threshold voltage before starting configuration.
This threshold voltage is labeled as VCCO2T in Table 74 of Module 3 and ranges from approximately 0.4V to 1.0V,
substantially lower than the SPI Flash PROM's minimum
voltage. Once all three FPGA supplies reach their
respective Power On Reset (POR) thresholds, the FPGA
starts the configuration process and begins initializing its
internal configuration memory. Initialization requires
approximately 1 ms (TPOR, minimum in Table 111 of Module 3, after which the FPGA de-asserts INIT_B, selects
the SPI Flash PROM, and starts sending the appropriate
read command. The SPI Flash PROM must be ready for
Table 56: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Vendor
SPI Flash PROM
Part Number
Data Sheet Minimum Time from VCC min to Select = Low
Symbol
Value
Units
STMicroelectronics
M25Pxx
TVSL
10
μs
Spansion
S25FLxxxA
tPU
10
ms
NexFlash
NX25xx
TVSL
10
μs
Macronix
MX25Lxxxx
tVSL
10
μs
Silicon Storage Technology
SST25LFxx
TPU-READ
10
μs
Programmable Microelectronics
Corporation
Pm25LVxxx
TVCS
50
μs
Atmel Corporation
AT45DBxxxD
tVCSL
30
μs
AT45DBxxxB
20
ms
X-Ref Target - Figure 55
Figure 55: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
FPGA VCCO_2 minimum
Power On Reset Voltage
(V
CCO2T)
SPI Flash PROM
minimum voltage
SPI Flash available for
read operations
SPI Flash
(t
VSL)
SPI Flash cannot be selected
FPGA initializes configuration
memory
3.3V Supply
FPGA accesses
SPI Flash PROM
Time
SPI Flash PROM must
be ready for FPGA
access, otherwise delay
FPGA configuration
DS312-2_50b_110206
(T
POR)
(VCCINT, VCCAUX
already valid)
PROM CS
delay