
Spartan-3 FPGA Family: Pinout Descriptions
72
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DS099-4 (v1.6) January 17, 2005
Product Specification
R
User I/Os by Bank
Table 34
indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks for the XC3S1000 in
the FG676 package. Similarly,
Table 35
shows how the
available user-I/O pins are distributed between the eight I/O
banks for the XC3S1500 in the FG676 package. Finally,
Table 36
shows the same information for the XC3S2000
and XC3S4000 in the FG676 package.
N/A
VCCAUX
VCCAUX
VCCAUX
V1
VCCAUX
N/A
VCCAUX
VCCAUX
VCCAUX
V26
VCCAUX
N/A
VCCINT
VCCINT
VCCINT
H8
VCCINT
N/A
VCCINT
VCCINT
VCCINT
H19
VCCINT
N/A
VCCINT
VCCINT
VCCINT
J9
VCCINT
N/A
VCCINT
VCCINT
VCCINT
J10
VCCINT
N/A
VCCINT
VCCINT
VCCINT
J17
VCCINT
N/A
VCCINT
VCCINT
VCCINT
J18
VCCINT
N/A
VCCINT
VCCINT
VCCINT
K9
VCCINT
N/A
VCCINT
VCCINT
VCCINT
K10
VCCINT
N/A
VCCINT
VCCINT
VCCINT
K17
VCCINT
N/A
VCCINT
VCCINT
VCCINT
K18
VCCINT
N/A
VCCINT
VCCINT
VCCINT
U9
VCCINT
N/A
VCCINT
VCCINT
VCCINT
U10
VCCINT
N/A
VCCINT
VCCINT
VCCINT
U17
VCCINT
N/A
VCCINT
VCCINT
VCCINT
U18
VCCINT
N/A
VCCINT
VCCINT
VCCINT
V9
VCCINT
N/A
VCCINT
VCCINT
VCCINT
V10
VCCINT
N/A
VCCINT
VCCINT
VCCINT
V17
VCCINT
N/A
VCCINT
VCCINT
VCCINT
V18
VCCINT
N/A
VCCINT
VCCINT
VCCINT
W8
VCCINT
N/A
VCCINT
VCCINT
VCCINT
W19
VCCINT
VCC
AUX
VCC
AUX
CCLK
CCLK
CCLK
AD26
CONFIG
DONE
DONE
DONE
AC24
CONFIG
Table 33:
FG676 Package Pinout
(Continued)
Bank
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
XC3S4000
Pin Name
FG676
Pin
Number
Type
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
HSWAP_EN
HSWAP_EN
HSWAP_EN
C2
CONFIG
M0
M0
M0
AE3
CONFIG
M1
M1
M1
AC3
CONFIG
M2
M2
M2
AF3
CONFIG
PROG_B
PROG_B
PROG_B
D3
CONFIG
TCK
TCK
TCK
B24
JTAG
TDI
TDI
TDI
C1
JTAG
TDO
TDO
TDO
D24
JTAG
TMS
TMS
TMS
A24
JTAG
Notes:
1.
XC3S4000 is pin compatible but uses alternate differential pairs on
six package balls.
Table 33:
FG676 Package Pinout
(Continued)
Bank
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
XC3S4000
Pin Name
FG676
Pin
Number
Type
Table 34:
User I/Os Per Bank for XC3S1000 in FG676 Package
Edge
I/O
Bank
Maximum
I/O
All Possible I/O Pins by Type
I/O
DUAL
DCI
VREF
GCLK
Top
0
49
40
0
2
5
2
1
50
41
0
2
5
2
Right
2
48
41
0
2
5
0
3
48
41
0
2
5
0
Bottom
4
50
35
6
2
5
2
5
50
35
6
2
5
2
Left
6
48
41
0
2
5
0
7
48
41
0
2
5
0