
Spartan-3 FPGA Family: Pinout Descriptions
DS099-4 (v1.6) January 17, 2005
Product Specification
www.xilinx.com
31
R
CP132 Footprint
Figure 9:
CP132 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.
44
I/O:
Unrestricted, general-purpose user I/O
12
DUAL:
Configuration pin, then possible
user I/O
11
VREF:
User I/O or input voltage reference for
bank
14
DCI:
User I/O or reference resistor input for
bank
8
GCLK:
User I/O, input, or global buffer
input
12
VCCO:
Output voltage supply for bank
7
CONFIG:
Dedicated configuration pins
4
JTAG:
Dedicated JTAG port pins
4
VCCINT:
Internal core voltage supply (+1.2V)
0
N.C.:
No unconnected pins in this package
12
GND:
Ground
4
VCCAUX:
Auxiliary voltage supply (+2.5V)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
TDI
PROG_B
VRP_0
VRP_7
VRP_6
VRN_4
VRN_2
VRN_1
VRP_1
VRP_2
VRP_4
VRP_3
VRN_3
VRN_6
VRN_7
VRN_0
VCCO_
TOP
VCCO_
TOP
VCCO_
TOP
VCCO_
RIGHT
VCCO_
RIGHT
VCCO_
RIGHT
VCCO_
BOTTOM
VCCO_
BOTTOM
VCCO_
BOTTOM
VCCO_
LEFT
VCCO_
LEFT
VCCO_
LEFT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
GCLK7
GCLK5
GCLK6
GCLK0
GCLK2
GCLK3
GCLK1
GCLK4
TMS
B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HSWAP_
EN
VCCINT
VCCINT
VCCINT
VCCINT
TCK
C
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TDO
D
L22N_7
L22P_7
L21P_7
L21N_7
L23P_7
L24P_7
L23N_7
L24N_7
L40P_7
L40P_6
VREF_6
L40N_7
VREF_7
L24N_6
VREF_6
L27N_5
VREF_5
L31N_5
D4
L31N_4
INIT_B
L31P_4
DOUT
BUSY
L30P_4
D3
L30N_4
D2
L27N_4
DIN
D0
L01P_4
L01N_4
L01N_3
L01P_3
L27P_4
D1
L40N_6
L24P_6
L23P_6
L22P_6
L27P_5
L22N_6
L20P_6
L20N_6
L01N_6
L01P_6
L01P_5
CS_B
L01N_5
RDWR_B
L28N_5
D6
L31P_5
D5
L28P_5
D7
L23N_6
E
F
G
VREF_3
VREF_3
VREF_2
VREF_2
VREF_1
VREF_0
VREF_4
H
J
K
L
M
M1
L20P_3
L24P_3
L22N_3
L23N_3
L20N_3
L23P_3
L40P_2
L23N_2
L40N_3
L24N_3
L24N_2
L20N_2
L01N_2
L01P_2
L01P_1
L01N_1
L21N_2
L27N_1
L27P_1
L31P_1
L30P_0
L27P_0
L27N_0
L30N_0
L31N_0
L31N_1
L01P_0
L01N_0
L01N_7
L01P_7
L31P_0
L32N_0
L32P_0
L32P_4
L32P_5
L32N_5
L32N_4
L32N_1
L32P_1
L28P_1
L28N_1
L20P_2
L40N_2
L24P_2
L23P_2
L21P_2
L40P_3
L22P_3
N
M0
P
M2
DONE
CCLK
VCCO_BOTTOM for Bottom Edge Outputs
VCCO_TOP for Top Edge Outputs
V
V
Bank 5
Bank 4
B
B
B
B
Bank 0
Bank 1
DS099-4_17_011005