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參數(shù)資料
| 型號(hào)： | XC3S1000-4TQ144C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 15/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-4TQ144C |
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Spartan-3 FPGA Family: Functional Description
8
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
The DCI feature operates independently for each of the
device’s eight banks. Each bank has an "N" reference pin
(VRN) and a "P" reference pin, (VRP), to calibrate driver
and termination resistance. Only when using a DCI stan-
dard on a given bank do these two pins function as VRN
and VRP. When not using a DCI standard, the two pins func-
tion as user I/Os. As shown in
Figure 3
, add an external ref-
erence resistor to pull the VRN pin up to V
CCO
and
another
reference resistor to pull the VRP pin down to GND. Both
resistors have the same value — commonly 50 Ohms —
with one-percent tolerance, which is either the characteristic
impedance of the line or twice that, depending on the DCI
standard in use. Standards having a symbol name that con-
tains the letters “DV2” use a reference resistor value that is
twice the line impedance. DCI adjusts the output driver
impedance to match the reference resistors’ value or half
that, according to the standard. DCI always adjusts the
on-chip termination resistors to directly match the reference
resistors’ value.
The rules guiding the use of DCI standards on banks are as
follows:
1.
No more than one DCI I/O standard with a Single
Termination is allowed per bank.
2.
No more than one DCI I/O standard with a Split
Termination is allowed per bank.
3.
Single Termination, Split Termination, Controlled-
Impedance Driver, and Controlled-Impedance Driver
with Half Impedance can co-exist in the same bank.
See also
The Organization of IOBs into Banks
, page 8
.
The Organization of IOBs into Banks
IOBs are allocated among eight banks, so that each side of
the device has two banks, as shown in
Figure 4
. For all
packages, each bank has independent V
REF
lines. For
example, V
REF
Bank 3 lines are separate from the V
REF
lines going to all other banks.
For the Very Thin Quad Flat Pack (VQ), Plastic Quad Flat
Pack (PQ), Fine Pitch Thin Ball Grid Array (FT), and Fine
Pitch Ball Grid Array (FG) packages, each bank has dedi-
cated V
CCO
lines. For example, the V
CCO
Bank 7 lines are
separate from the V
CCO
lines going to all other banks. Thus,
Spartan-3 devices in these packages support eight inde-
pendent V
CCO
supplies.
In contrast, the 144-pin Thin Quad Flat Pack (TQ144) pack-
age ties V
CCO
together internally for the pair of banks on
each side of the device. For example, the V
CCO
Bank 0 and
the V
CCO
Bank 1 lines are tied together. The interconnected
bank-pairs are 0/1, 2/3, 4/5, and 6/7. As a result, Spartan-3
devices in the TQ144 package support four independent
V
CCO
supplies.
Spartan-3 Compatibility
Within the Spartan-3 family, all devices are pin-compatible
by package. When the need for future logic resources out-
grows the capacity of the Spartan-3 device in current use, a
larger device in the same package can serve as a direct
replacement. Larger devices may add extra V
REF
and V
CCO
lines to support a greater number of I/Os. In the larger
device, more pins can convert from user I/Os to V
REF
lines.
Also, additional V
CCO
lines are bonded out to pins that were
“not connected” in the smaller device. Thus, it is important
to plan for future upgrades at the time of the board’s initial
design by laying out connections to the extra pins.
The Spartan-3 family is not pin-compatible with any previ-
ous Xilinx FPGA family.
Rules Concerning Banks
When assigning I/Os to banks, it is important to follow the
following V
CCO
rules:
1.
Leave no V
CCO
pins unconnected on the FPGA.
2.
Set all V
CCO
lines associated with the (interconnected)
bank to the same voltage level.
3.
The V
CCO
levels used by all standards assigned to the
I/Os of the (interconnected) bank(s) must agree. The
Xilinx development software checks for this. Tables
4
,
5
,
and
6
describe how different standards use the V
CCO
supply.
Figure 3:
Connection of Reference Resistors (R
REF
)
DS099-2_04_082104
VCCO
VRN
VRP
One of eight
I/O Banks
R
REF
(1%)
R
REF
(1%)
Figure 4:
Spartan-3 I/O Banks (top view)
DS099-2_03_082104
Bank 0
Bank 1
Bank 5
Bank 4
B
B
B
B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000 | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4TQG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4TQG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
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