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參數(shù)資料
| 型號(hào)： | XC3S1000-4CP132C |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PBGA132 |
| 封裝： | CSP-132 |
| 文件頁(yè)數(shù)： | 12/198頁(yè) |
| 文件大小： | 1605K |
| 代理商： | XC3S1000-4CP132C |
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Spartan-3 FPGA Family: Functional Description
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
www.xilinx.com
5
R
output voltage swing for all standards except GTL and
GTLP.
All single-ended standards except the LVCMOS, LVTTL,
and PCI varieties require a Reference Voltage (V
REF
) to
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use such a signal standard, a few specifically
reserved I/O pins on the same bank automatically convert
to V
REF
inputs. When using one of the LVCMOS standards,
these pins remain I/Os because the V
CCO
voltage biases
the input-switching threshold, so there is no need for V
REF
.
Select the V
CCO
and V
REF
levels to suit the desired sin-
gle-ended standard according to
Table 4
.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling (e.g.,
Common-Mode Rejection) properties of these standards
permit exceptionally high data transfer rates. This section
introduces the differential signaling capabilities of Spartan-3
devices.
Each device-package combination designates specific I/O
pairs that are specially optimized to support differential
standards. A unique “L-number”, part of the pin name, iden-
tifies the line-pairs associated with each bank (see Module
4:
Pinout Descriptions
). For each pair, the letters “P” and
“N” designate the true and inverted lines, respectively. For
example, the pin names IO_L43P_7 and IO_L43N_7 indi-
cate the true and inverted lines comprising the line pair L43
on Bank 7. The V
CCO
lines provide current to the outputs.
The V
REF
lines are not used. Select the V
CCO
level to suit
the desired differential standard according to
Table 5
.
The need to supply V
REF
and V
CCO
imposes constraints on
which standards can be used in the same bank. See
The
Organization of IOBs into Banks
section for additional
guidelines concerning the use of the V
CCO
and V
REF
lines.
Digitally Controlled Impedance (DCI)
When the round-trip delay of an output signal — i.e., from
output to input and back again — exceeds rise and fall
times, it is common practice to add termination resistors to
the line carrying the signal. These resistors effectively
match the impedance of a device’s I/O to the characteristic
impedance of the transmission line, thereby preventing
reflections that adversely affect signal integrity. However,
with the high I/O counts supported by modern devices, add-
ing resistors requires significantly more components and
board area. Furthermore, for some packages — e.g., ball
grid arrays — it may not always be possible to place resis-
tors close to pins.
DCI answers these concerns by providing two kinds of
on-chip terminations: Parallel terminations make use of an
integrated resistor network. Series terminations result from
controlling the impedance of output drivers. DCI actively
adjusts both parallel and series terminations to accurately
match the characteristic impedance of the transmission line.
This adjustment process compensates for differences in I/O
impedance that can result from normal variation in the
ambient temperature, the supply voltage and the manufac-
Table 4:
Single-Ended I/O Standards (Values in Volts)
V
CCO
For
Outputs
Inputs
GTL
Note 2
Note 2
GTLP
Note 2
Note 2
HSTL_I
1.5
HSTL_III
1.5
HSTL_I_18
1.8
HSTL_II_18
1.8
HSTL_III_18
1.8
LVCMOS12
1.2
1.2
LVCMOS15
1.5
1.5
LVCMOS18
1.8
1.8
LVCMOS25
2.5
2.5
LVCMOS33
3.3
3.3
LVTTL
3.3
3.3
PCI33_3
3.0
3.0
SSTL18_I
1.8
Signal
Standard
V
REF
for
Inputs
(1)
0.8
1
0.75
0.9
0.9
0.9
1.1
-
-
-
-
-
-
-
0.9
Board
Termination
Voltage (V
TT
)
1.2
1.5
0.75
1.5
0.9
0.9
1.8
-
-
-
-
-
-
-
0.9
For
-
-
-
-
-
-
SSTL2_I
SSTL2_II
2.5
2.5
-
-
1.25
1.25
1.25
1.25
Notes:
1.
Banks 4 and 5 of any Spartan-3 device in a VQ100 package
do not support signal standards using V
REF
.
The V
level used for the GTL and GTLP standards must
be no lower than the termination voltage (V
TT
), nor can it be
lower than the voltage at the I/O pad.
See
Table 6
for a listing of the single-ended DCI standards.
2.
3.
Table 5:
Differential I/O Standards
Signal Standard
LDT_25 (ULVDS_25)
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
Notes:
1.
See
Table 6
for a listing of the differential DCI standards.
V
CCO
(Volts)
For
Outputs
2.5
2.5
2.5
2.5
2.5
2.5
V
REF
for
Inputs
(Volts)
-
-
-
-
-
-
For
Inputs
-
-
-
-
-
-
Table 4:
Single-Ended I/O Standards (Values in Volts)
V
CCO
For
Outputs
Inputs
Signal
Standard
V
REF
for
Inputs
(1)
Board
Termination
Voltage (V
TT
)
For
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208I | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4CP132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4CPG132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4FG1156C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S1000-4FG1156I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
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