參數(shù)資料
型號(hào)： XC3190A-3PQ160C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 28/76頁(yè)
文件大?。?/td> 0K
描述： IC LOGIC CL ARRAY 9000GAT 160PQF
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝： 24
系列： XC3000A/L
LAB/CLB數(shù)： 320
RAM 位總計(jì)： 64160
輸入/輸出數(shù)： 138
門(mén)數(shù)： 6000
電源電壓： 4.25 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
其它名稱(chēng)： 122-1047
R
XC3000 Series Field Programmable Gate Arrays
7-36
November 9, 1998 (Version 3.1)
Power
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated VCC and ground ring sur-
rounding the logic array provides power to the I/O drivers.
An independent matrix of VCC and groundlines supplies the
interior logic of the device. This power distribution grid pro-
vides a stable supply and ground for all internal logic, pro-
viding the external package power pins are all connected
and appropriately decoupled. Typically a 0.1-
F capacitor
connected near the VCC and ground pins will provide ade-
quate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driv-
ing as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.
1.00
0.80
0.60
0.40
0.20
SPECIFIED WORST-CASE VALUES
MAX
CO
MMERCIAL
(4.75
V)
MAX
MILITARY
(4.5
V)
– 55
MIN MILITARY
(5.5 V)
MIN COMMERCIAL
(4.75 V)
MIN COMMERCIAL
(5.25 V)
TYPICAL COMMERCIAL
(+ 5.0 V, 25
°C)
TYPICAL MILITARY
TEMPERATURE (
°C)
– 40
– 20
0
25
40
70
80
100
125
NORMALIZED
DELAY
X6094
MIN MILITARY
(4.5 V)
Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
System
Clock
(MHz)
250
200
150
100
50
3 CLBs
(3-12)
4 CLBs
(4-16)
2 CLBs
(2-8)
1 CLB
(1-4)
XC3100A-3
XC3000A--6
CLB Levels:
Gate Levels:
300
Toggle
Rate
0
X7065
Figure 33: Clock Rate as a Function of Logic
Complexity (Number of Combinational Levels between
Flip-Flops)
Product Obsolete or Under Obsolescence
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參數(shù)描述
XC3190A-3PQ160C0262 制造商:Xilinx 功能描述:
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XC3190A-3PQ208C 制造商:Xilinx 功能描述:
XC3190A-3PQ208I 制造商:Xilinx 功能描述:
XC3190A-3TQ144C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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