參數(shù)資料
型號： XC3000LSERIES
廠商： Xilinx, Inc.
英文描述： Field Programmable Gate Arrays
中文描述： 現(xiàn)場可編程門陣列
文件頁數(shù)： 24/76頁
文件大?。?/td> 731K
代理商： XC3000LSERIES
R
XC3000 Series Field Programmable Gate Arrays
7-32
November 9, 1998 (Version 3.1)
Notes:
1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA.
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
Figure 30: Slave Serial Mode Programming Switching Characteristics
4 TCCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 TCCO
5 TCCL
2 TCCD
1 TDCC
DIN
CCLK
DOUT
(Output)
X5379
Description
Symbol
Min
Max
Units
CCLK
To DOUT
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
3
1
2
4
5
TCCO
TDCC
TCCD
TCCH
TCCL
FCC
60
0
0.05
100
5.0
10
ns
s
MHz
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