Virtex-II Platform FPGAs: DC and Switching Characteristics
R
DS031-3 (v3.5) November 5, 2007
Module 3 of 4
Product Specification
16
HSTL, Class II, 1.8V
HSTL_II_18
TOHSTL_II_18
–0.17
–0.18
–0.20
ns
HSTL, Class III, 1.8V
HSTL_III_18
TOHSTL_III_18
–0.16
–0.18
ns
HSTL, Class IV, 1.8V
HSTL_IV_18
TOHSTL_IV_18
–0.39
–0.40
–0.44
ns
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL18_I
TOSSTL18_I
0.20
0.22
ns
SSTL, Class II, 1.8V
SSTL18_II
TOSSTL18_II
–0.05
–0.06
ns
SSTL, Class I, 2.5V
SSTL2_I
TOSSTL2_I
0.21
0.22
0.24
ns
SSTL, Class II, 2.5V
SSTL2_II
TOSSTL2_II
–0.15
–0.16
–0.18
ns
SSTL, Class I, 3.3V
SSTL3_I
TOSSTL3_I
0.29
0.30
0.33
ns
SSTL, Class II, 3.3V
SSTL3_II
TOSSTL3_II
–0.05
ns
AGP-2X/AGP (Accelerated Graphics Port)
AGP
TOAGP
–0.27
–0.28
–0.31
ns
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI_33
TOLVDCI_33
0.74
0.77
0.84
ns
LVDCI, 2.5V
LVDCI_25
TOLVDCI_25
0.78
0.80
0.88
ns
LVDCI, 1.8V
LVDCI_18
TOLVDCI_18
0.84
0.87
0.95
ns
LVDCI, 1.5V
LVDCI_15
TOLVDCI_15
1.82
1.88
2.06
ns
LVDCI, 3.3V, Half-Impedance
LVDCI_DV2_33
TOLVDCI_DV2_33
0.12
0.13
ns
LVDCI, 2.5V, Half-Impedance
LVDCI_DV2_25
TOLVDCI_DV2_25
0.03
ns
LVDCI, 1.8V, Half-Impedance
LVDCI_DV2_18
TOLVDCI_DV2_18
0.42
0.43
0.48
ns
LVDCI, 1.5V, Half-Impedance
LVDCI_DV2_15
TOLVDCI_DV2_15
1.20
1.23
1.36
ns
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI_15
TOHSLVDCI_15
1.82
1.88
2.06
ns
HSLVDCI, 1.8V
HSLVDCI_18
TOHSLVDCI_18
1.05
1.08
1.24
ns
HSLVDCI, 2.5V
HSLVDCI_25
TOHSLVDCI_25
0.78
0.80
0.88
ns
HSLVDCI, 3.3V
HSLVDCI_33
TOHSLVDCI_33
0.74
0.77
0.84
ns
GTL (Gunning Transceiver Logic) with DCI
GTL_DCI
TOGTL_DCI
–0.31
–0.32
–0.35
ns
GTL Plus with DCI
GTLP_DCI
TOGTLP_DCI
–0.15
–0.16
–0.17
ns
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL_I_DCI
TOHSTL_I_DCI
0.23
0.26
ns
HSTL, Class II, with DCI
HSTL_II_DCI
TOHSTL_II_DCI
0.06
0.07
ns
HSTL, Class III, with DCI
HSTL_III_DCI
TOHSTL_III_DCI
–0.17
–0.18
–0.20
ns
HSTL, Class IV, with DCI
HSTL_IV_DCI
TOHSTL_IV_DCI
–0.46
–0.47
–0.52
ns
HSTL, Class I, 1.8V, with DCI
HSTL_I_DCI_18
TOHSTL_I_DCI_18
0.05
0.06
ns
HSTL, Class II, 1.8V, with DCI
HSTL_II_DCI_18
TOHSTL_II_DCI_18
–0.03
ns
HSTL, Class III, 1.8V, with DCI
HSTL_III_DCI_18
TOHSTL_III_DCI_18
–0.14
–0.16
ns
HSTL, Class IV, 1.8V, with DCI
HSTL_IV_DCI_18
TOHSTL_IV_DCI_18
–0.41
–0.42
–0.47
ns
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL18_I_DCI
TOSSTL18_I_DCI
0.36
0.37
0.40
ns
SSTL, Class II, 1.8V, with DCI
SSTL18_II_DCI
TOSSTL18_II_DCI
0.06
0.07
ns
SSTL, Class I, 2.5V, with DCI
SSTL2_I_DCI
TOSSTL2_I_DCI
0.12
0.13
0.14
ns
SSTL, Class II, 2.5V, with DCI
SSTL2_II_DCI
TOSSTL2_II_DCI
–0.10
–0.11
ns
SSTL, Class I, 3.3V, with DCI
SSTL3_I_DCI
TOSSTL3_I_DCI
0.15
0.16
0.17
ns
SSTL, Class II, 3.3V, with DCI
SSTL3_II_DCI
TOSSTL3_II_DCI
0.08
0.09
ns
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
IOSTANDARD
Attribute
Timing
Parameter
Speed Grade
Units
-6
-5
-4