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參數(shù)資料
| 型號： | XC2S600E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 平臺Flash在系統(tǒng)可編程配置方案管理系統(tǒng) |
| 文件頁數(shù)： | 6/46頁 |
| 文件大小： | 525K |
| 代理商： | XC2S600E |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
6
R
logic 0. IR[2] is unused, and is set to '0'. The remaining bits
IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
XCFxxP Instruction Register (16 bits wide)
The Instruction Register (IR) for the XCFxxP PROM is sixteen
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in
Table 8, page 6
.
The instruction capture pattern shifted out of the XCFxxP
device includes IR[15:0]. IR[15:9] are reserved bits and are
set to a logic 0. The ISC Error field, IR[8:7], contains a
10
when an ISC operation is a success; otherwise a
01
when
an In-System Configuration (ISC) operation fails. The
Erase/Program (ER/PROG) Error field, IR[6:5], contains a
10
when an erase or program operation is a success;
otherwise a
01
when an erase or program operation fails.
The Erase/Program (ER/PROG) Status field, IR[4], contains
a logic 0 when the device is busy performing an erase or
programming operation; otherwise, it contains a logic 1. The
ISC Status field, IR[3], contains logic 1 if the device is
currently in In-System Configuration (ISC) mode; otherwise,
it contains logic 0. The DONE field, IR[2], contains logic 1 if
the sampled design revision has been successfully
programmed; otherwise, a logic 0 indicates incomplete
programming. The remaining bits IR[1:0] are set to
01
as
defined by IEEE Std. 1149.1.
Table 6:
Platform Flash PROM Boundary Scan Instructions
Boundary-Scan Command
XCFxxS IR[7:0]
(hex)
XCFxxP IR[15:0]
(hex)
Instruction Description
Required Instructions
BYPASS
FF
FFFF
Enables BYPASS
SAMPLE/PRELOAD
01
0001
Enables boundary-scan SAMPLE/PRELOAD operation
EXTEST
00
0000
Enables boundary-scan EXTEST operation
Optional Instructions
CLAMP
FA
00FA
Enables boundary-scan CLAMP operation
HIGHZ
FC
00FC
Places all outputs in high-impedance state
simultaneously
IDCODE
FE
00FE
Enables shifting out 32-bit IDCODE
USERCODE
FD
00FD
Enables shifting out 32-bit USERCODE
Platform Flash PROM
Specific Instructions
CONFIG
EE
00EE
Initiates FPGA configuration by pulsing CF pin Low
once. (For the XCFxxP this command also resets the
selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision
selection bits.)
(1)
Notes:
1.
For more information see
"Initiating FPGA Configuration," page 13
.
Table 7:
XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
TDI
→
IR[7:5]
IR[4]
IR[3]
IR[2]
IR[1:0]
→
TDO
Reserved
ISC Status
Security
0
0 1
Table 8:
XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
TDI
→
IR[15:9]
IR[8:7]
IR[6:5]
IR[4]
IR[3]
IR[2]
IR[1:0]
→
TDO
Reserved
ISC Error
ER/PROG
Error
ER/PROG
Status
ISC Status
DONE
0 1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S600E-6FG456C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-6FG456I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| XC2S600E-6FG456Q | 功能描述:IC FPGA SPARTAN-IIE 456FPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2S600E-6FG676C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| XC2S600E-6FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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