- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4281 > XC2S200-5FGG256C (Xilinx Inc)IC SPARTAN-II FPGA 200K 256-FBGA PDF資料下載
參數(shù)資料
| 型號： | XC2S200-5FGG256C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 27/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPARTAN-II FPGA 200K 256-FBGA |
| 標準包裝： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 1176 |
| 邏輯元件/單元數(shù)： | 5292 |
| RAM 位總計： | 57344 |
| 輸入/輸出數(shù)： | 176 |
| 門數(shù)： | 200000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-FBGA（17x17） |
| 其它名稱： | 122-1310 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
33
R
Port Signals
Each block RAM port operates independently of the others
while accessing the same set of 4096 memory cells.
Table 12 describes the depth and width aspect ratios for the
block RAM memory.
Clock—CLK[A|B]
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time
referenced to the CLK pin.
Enable—EN[A|B]
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the
memory cells.
Write Enable—WE[A|B]
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the
contents of the memory cells referenced by the address bus
reflect on the data out bus.
Reset—RST[A|B]
The reset pin forces the data output bus latches to zero
synchronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
Address Bus—ADDR[A|B]<#:0>
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in Table 12.
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width,
as shown in Table 12.
Data Output Bus—DO[A|B]<#:0>
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in Table 12.
Inverting Control Pins
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration
option.
Address Mapping
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port. The physical RAM location addressed for a particular
width are described in the following formula (of interest only
when the two ports use different aspect ratios).
Start = ([ADDRport + 1] * Widthport) – 1
End = ADDRport * Widthport
Table 13 shows low order address mapping for each port
width.
RAMB4_S4
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
4N/A
4
8
16
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
8N/A
8
16
RAMB4_S16
RAMB4_S16_S16
16
N/A
16
Table 12: Block RAM Port Aspect Ratios
Width
Depth
ADDR Bus
Data Bus
1
4096
ADDR<11:0>
DATA<0>
2
2048
ADDR<10:0>
DATA<1:0>
4
1024
ADDR<9:0>
DATA<3:0>
8
512
ADDR<8:0>
DATA<7:0>
16
256
ADDR<7:0>
DATA<15:0>
Table 11: Available Library Primitives
Primitive
Port A Width
Port B Width
Table 13: Port Address Mapping
Port
Widt
h
Port
Addresses
1
4095...
1
5
1
4
1
3
1
2
1
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
2
2047...
07
06
05
04
03
02
01
00
4
1023...
03
02
01
00
8
511...
01
00
16
255...
00
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC2S200-5FG256C | IC FPGA 2.5V C-TEMP 256-FBGA |
| XC6SLX16-L1FT256I | IC FPGA SPARTAN 6 256FTGBGA |
| 554725-5 | CONN CHAMP INNER FERRULE .450 |
| AMC40DRTN | CONN EDGECARD 80POS .100 DIP SLD |
| AMC40DRTH | CONN EDGECARD 80POS .100 DIP SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S200-5FGG256I | 功能描述:IC SPARTAN-II FPGA 200K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S200-5FGG456C | 功能描述:IC SPARTAN-II FPGA 200K 456-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S200-5FGG456C4124 | 制造商:Xilinx 功能描述: |
| XC2S200-5FGG456I | 功能描述:IC SPARTAN-II FPGA 200K 456-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S200-5PQ208C | 功能描述:IC FPGA 2.5V 1176 CLB'S 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
發(fā)布緊急采購，3分鐘左右您將得到回復。