參數(shù)資料
型號： XC2S200-5FG256C
廠商： Xilinx Inc
文件頁數(shù)： 17/99頁
文件大?。?/td> 0K
描述： IC FPGA 2.5V C-TEMP 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-II
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計(jì)： 57344
輸入/輸出數(shù)： 176
門數(shù)： 200000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
24
R
Multiple Spartan-II FPGAs can be configured using the
Slave Parallel mode, and be made to start-up
simultaneously. To configure multiple devices in this way,
wire the individual CCLK, Data, WRITE, and BUSY pins of
all the devices in parallel. The individual devices are loaded
separately by asserting the CS pin of each device in turn
and writing the appropriate data. Sync-to-DONE start-up
timing is used to ensure that the start-up sequence does not
begin until all the FPGAs have been loaded. See "Start-up,"
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 19, page 25 shows a flowchart of the write sequence
used to load data into the Spartan-II FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 11, page 18. The timing for write operations is shown
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or de-asserted. Otherwise an abort
will be initiated, as in the next section.
1.
Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2.
On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3.
Repeat steps 1 and 2 until all the data has been sent.
4.
De-assert CS and WRITE.
Figure 18: Slave Parallel Configuration Circuit Diagram
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONEINIT
CCLK
DATA[7:0]
WRITE
BUSY
CS(0)
330
Ω
Spartan-II
FPGA
DONE
INIT
PROGRAM
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONEINIT
CS(1)
Spartan-II
FPGA
DS001_18_060608
GND
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S200-5FG256C-ES 制造商:Xilinx 功能描述:2S200-5FG256C-ES
XC2S200-5FG256I 功能描述:IC FPGA 2.5V I-TEMP 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S200-5FG256I-0744 制造商:Xilinx 功能描述:
XC2S2005FG456C 制造商:Xilinx 功能描述:
XC2S200-5FG456C 功能描述:IC FPGA 2.5V 1176 CLB'S 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
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