參數(shù)資料
型號： XC2S100-5TQG144C
廠商： Xilinx Inc
文件頁數(shù)： 68/99頁
文件大?。?/td> 0K
描述： IC SPARTAN-II FPGA 100K 144-TQFP
標準包裝： 60
系列： Spartan®-II
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計： 40960
輸入/輸出數(shù)： 92
門數(shù)： 100000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
產(chǎn)品目錄頁面： 599 (CN2011-ZH PDF)
其它名稱： 122-1305
Spartan-II FPGA Family: Pinout Tables
DS001-4 (v2.8) June 13, 2008
Module 4 of 4
Product Specification
70
R
Note: Some early versions of Spartan-II devices, including
the XC2S15 and XC2S30 ES devices and the XC2S150
with date code 0045 or earlier, included a power-down pin.
For more information, see Answer Record 10500.
VCCO Banks
Some of the I/O standards require specific VCCO voltages.
These voltages are externally connected to device pins that
serve groups of IOBs, called banks. Eight I/O banks result
from separating each edge of the FPGA into two banks (see
Figure 3 in Module 2). Each bank has multiple VCCO pins
which must be connected to the same voltage. In the
smaller packages, the VCCO pins are connected between
banks, effectively reducing the number of independent
banks available (see Table 37). These interconnected
banks are shown in the Pinout Tables with VCCO pads for
multiple banks connected to the same pin.
Package Overview
Table 36 shows the six low-cost, space-saving production
package styles for the Spartan-II family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “CS144” package becomes
“CSG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in Table 38.
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table 38.
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Table 36: Spartan-II Family Package Options
Package
Leads
Type
Maximum
I/O
Lead Pitch
(mm)
Footprint
Area (mm)
Height
(mm)
Mass(1)
(g)
VQ100 / VQG100
100
Very Thin Quad Flat Pack (VQFP)
60
0.5
16 x 16
1.20
0.6
TQ144 / TQG144
144
Thin Quad Flat Pack (TQFP)
92
0.5
22 x 22
1.60
1.4
CS144 / CSG144
144
Chip Scale Ball Grid Array (CSBGA)
92
0.8
12 x 12
1.20
0.3
PQ208 / PQG208
208
Plastic Quad Flat Pack (PQFP)
140
0.5
30.6 x 30.6
3.70
5.3
FG256 / FGG256
256
Fine-pitch Ball Grid Array (FBGA)
176
1.0
17 x 17
2.00
0.9
FG456 / FGG456
456
Fine-pitch Ball Grid Array (FBGA)
284
1.0
23 x 23
2.60
2.2
Notes:
1.
Package mass is
±10%.
Table 37: Independent VCCO Banks Available
Package
VQ100
PQ208
CS144
TQ144
FG256
FG456
Independent Banks
1
4
8
Table 38: Xilinx Package Documentation
Package
Drawing
MDDS
VQ100
VQG100
TQ144
TQG144
CS144
CSG144
PQ208
PQG208
FG256
FGG256
FG456
FGG456
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