參數資料
型號: XC2S100-5TQG144C
廠商: Xilinx Inc
文件頁數: 42/99頁
文件大?。?/td> 0K
描述: IC SPARTAN-II FPGA 100K 144-TQFP
標準包裝: 60
系列: Spartan®-II
LAB/CLB數: 600
邏輯元件/單元數: 2700
RAM 位總計: 40960
輸入/輸出數: 92
門數: 100000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
產品目錄頁面: 599 (CN2011-ZH PDF)
其它名稱: 122-1305
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
47
R
SSTL2_I
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 49. DC voltage specifications
appear in Table 27 for the SSTL2_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
SSTL2 Class II
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in Figure 50. DC voltage specifications
appear in Table 28 for the SSTL2_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
Figure 49: Terminated SSTL2 Class I
Table 27: SSTL2_I Voltage Specifications
Parameter
Min
Typ
Max
VCCO
2.3
2.5
2.7
VREF = 0.5 × VCCO
1.15
1.25
1.35
VTT = VREF + N(1)
1.11
1.25
1.39
VIH ≥ VREF + 0.18
1.33
1.43
3.0(2)
VIL ≤ VREF – 0.18
–0.3(3)
1.07
1.17
VOH ≥ VREF + 0.61
1.76
-
VOL ≤ VREF – 0.61
-
0.74
IOH at VOH (mA)
–7.6
-
IOL at VOL (mA)
7.6
-
Notes:
1.
N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2.
VIH maximum is VCCO + 0.3.
3.
VIL minimum does not conform to the formula.
VREF = 1.25V
VCCO = 2.5V
50
Ω
Z = 50
SSTL2 Class I
DS001_49_061200
VTT = 1.25V
25
Ω
Figure 50: Terminated SSTL2 Class II
Table 28: SSTL2_II Voltage Specifications
Parameter
Min
Typ
Max
VCCO
2.3
2.5
2.7
VREF = 0.5 × VCCO
1.15
1.25
1.35
VTT = VREF + N(1)
1.11
1.25
1.39
VIH ≥ VREF + 0.18
1.33
1.43
3.0(2)
VIL ≤ VREF – 0.18
–0.3(3)
1.07
1.17
VOH ≥ VREF + 0.8
1.95
-
VOL ≤ VREF - 0.8
-
0.55
IOH at VOH (mA)
–15.2
-
IOL at VOL (mA)
15.2
-
Notes:
1.
N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2.
VIH maximum is VCCO + 0.3.
3.
VIL minimum does not conform to the formula.
VREF = 1.25V
VCCO = 2.5V
50
Ω
Z = 50
SSTL2 Class II
DS001_50_061200
VTT = 1.25V
50
Ω
VTT = 1.25V
25
Ω
相關PDF資料
PDF描述
TACR476M003H CAP TANT 47UF 3V 20% 0805
XC3S400A-4FTG256C IC SPARTAN-3A FPGA 400K 256FTBGA
XC3S200AN-4FTG256C IC SPARTAN-3AN FPGA 200K 256FTBG
TACR476M002R CAP TANT 47UF 2V 20% 0805
RMC44DRYI CONN EDGECARD 88POS DIP .100 SLD
相關代理商/技術參數
參數描述
XC2S100-5TQG144I 制造商:Xilinx 功能描述:FPGA SPARTAN-II 100K GATES 2700 CELLS 263MHZ 2.5V 144TQFP EP - Trays 制造商:Xilinx 功能描述:XLXXC2S100-5TQG144I IC SYSTEM GATE
XC2S100-5VQ100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S100-5VQ100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S100-5VQG100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S100-5VQG100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family