參數(shù)資料
型號(hào)： XA3S1200E-4FTG256Q
廠商： Xilinx Inc
文件頁(yè)數(shù)： 36/37頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN3E 1200K 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3E XA
LAB/CLB數(shù)： 8672
邏輯元件/單元數(shù)： 19512
RAM 位總計(jì)： 516096
輸入/輸出數(shù)： 190
門(mén)數(shù)： 1200000
電源電壓： 1.14 V ~ 1.26 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
DS635 (v2.0) September 9, 2009
Product Specification
8
R
DC Specifications
General DC Characteristics for I/O Pins
Table 6: General Recommended Operating Conditions
Symbol
Description
Min
Nominal
Max
Units
TJ
Junction temperature
I-Grade
–40
25
100
° C
Q-Grade
–40
25
125
° C
VCCINT
Internal supply voltage
1.140
1.200
1.260
V
VCCO(1)
Output driver supply voltage
1.100
-
3.465
V
VCCAUX
Auxiliary supply voltage
2.375
2.500
2.625
V
ΔVCCAUX(2)
Voltage variance on VCCAUX when using a DCM
-
-10
mV/ms
VIN(3,4,5,6)
Input voltage extremes to avoid
turning on I/O protection diodes
I/O, Input-only, and
Dual-Purpose pins(3)
–0.5
–
VCCO + 0.5
V
Dedicated pins(4)
–0.5
–
VCCAUX + 0.5
V
TIN
Input signal transition time(7)
––
500
ns
Notes:
1.
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 9 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 11 lists that specific to the differential standards.
2.
Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms.
3.
Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ VCCO rails. Meeting the VIN limit ensures that the
internal diode junctions that exist between these pins and their associated VCCO and GND rails do not turn on. See Absolute Maximum
Ratings in DS312).
4.
All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures
that the internal diode junctions that exist between each of these pins and the VCCAUX and GND rails do not turn on.
5.
Input voltages outside the recommended range is permissible provided that the IIK input clamp diode rating is met and no more than 100 pins
exceed the range simultaneously. See Absolute Maximum Ratings in DS312).
6.
See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins."
7.
Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.
Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
Typ
Max
Units
IL
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
–
+10
μA
IRPU(2)
Current through pull-up resistor at
User I/O, Dual-Purpose, Input-only,
and Dedicated pins
VIN = 0V, VCCO = 3.3V
–0.36
–
–1.24
mA
VIN = 0V, VCCO = 2.5V
–0.22
–
–0.80
mA
VIN = 0V, VCCO = 1.8V
–0.10
–
–0.42
mA
VIN = 0V, VCCO = 1.5V
–0.06
–
–0.27
mA
VIN = 0V, VCCO = 1.2V
–0.04
–
–0.22
mA
RPU(2)
Equivalent pull-up resistor value at
User I/O, Dual-Purpose, Input-only,
and Dedicated pins (based on IRPU
per Note 2)
VIN = 0V, VCCO = 3.0V to 3.465V
2.4
–
10.8
k
Ω
VIN = 0V, VCCO = 2.3V to 2.7V
2.7
–
11.8
k
Ω
VIN = 0V, VCCO = 1.7V to 1.9V
4.3
–
20.2
k
Ω
VIN = 0V, VCCO =1.4V to 1.6V
5.0
–
25.9
k
Ω
VIN = 0V, VCCO = 1.14V to 1.26V
5.5
–
32.0
k
Ω
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