FN8221.3 March 8, 2006 Register Listing ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION 0x01 SYNC Status (read only) 0" />
參數(shù)資料
型號(hào): X98027L128-3.3-Z
廠商: Intersil
文件頁(yè)數(shù): 3/29頁(yè)
文件大?。?/td> 0K
描述: IC TRPL VID DIGITIZER 128MQFP
標(biāo)準(zhǔn)包裝: 660
類型: 視頻數(shù)字轉(zhuǎn)換器
應(yīng)用: 監(jiān)控器,電視
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
11
FN8221.3
March 8, 2006
Register Listing
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(s)
FUNCTION NAME
DESCRIPTION
0x01
SYNC Status
(read only)
0
HSYNC1 Active
0: HSYNC1 is Inactive
1: HSYNC1 is Active
1
HSYNC2 Active
0: HSYNC2 is Inactive
1: HSYNC2 is Active
2
VSYNC1 Active
0: VSYNC1 is Inactive
1: VSYNC1 is Active
3
VSYNC2 Active
0: VSYNC2 is Inactive
1: VSYNC2 is Active
4
SOG1 Active
0: SOG1 is Inactive
1: SOG1 is Active
5
SOG2 Active
0: SOG2 is Inactive
1: SOG2 is Active
6
PLL Locked
0: PLL is unlocked
1: PLL is locked to incoming HSYNC
7
CSYNC Detected at
Sync Splitter Output
0: Composite Sync signal not detected
1: Composite Sync signal is detected
0x02
SYNC Polarity
(read only)
0
HSYNC1
Polarity
0: HSYNC1 is Active High
1: HSYNC1 is Active Low
1
HSYNC2
Polarity
0: HSYNC2 is Active High
1: HSYNC2 is Active Low
2VSYNC1
Polarity
0: VSYNC1 is Active High
1: VSYNC1 is Active Low
3VSYNC2
Polarity
0: VSYNC2 is Active High
1: VSYNC2 is Active Low
4
HSYNC1
Trilevel
0: HSYNC1 is Standard Sync
1: HSYNC1 is Trilevel Sync
5
HSYNC2
Trilevel
0: HSYNC2 is Standard Sync
1: HSYNC2 is Trilevel Sync
7:6
N/A
Returns 0
0x03
HSYNC Slicer (0x44)
2:0
HSYNC1 Threshold
000 = lowest (0.4V) All values referred to
100 = default (2.0V) voltage at HSYNC input
111 = highest (3.2V) pin, 240mV hysteresis
3
Reserved
Set to 00
6:4
HSYNC2 Threshold
See HSYNC1
7
Disable Glitch Filter
0: HSYNC/VSYNC Digital Glitch Filter Enabled (default)
1: HSYNC/VSYNC Digital Glitch Filter Disabled
0x04
SOG Slicer (0x08)
3:0
SOG1 and SOG2
Threshold
0x0 = lowest (0mV)
40mV hysteresis at
0x8 = default (160mV) all settings
0xF = highest (300mV) 20mV step size
4
SOG Filter
Enable
0: SOG low pass filter disabled (default)
1: SOG low pass filter enabled, 14MHz corner
5SOG Hysteresis
Disable
0: 40mV SOG hysteresis enabled
1: 40mV SOG hysteresis disabled (default)
7:6
Reserved
Set to 00.
X98027
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