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參數(shù)資料
| 型號： | X98024 |
| 廠商： | Intersil Corporation |
| 英文描述： | 240MHz Triple Video Digitizer with Digital PLL |
| 中文描述： | 240MHz的三路視頻數(shù)字化與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 295K |
| 代理商： | X98024 |
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9
FN8220.0
June 6, 2005
Pin Descriptions
SYMBOL
PIN
DESCRIPTION
R
IN
1
7
Analog input. Red channel 1. DC couple or AC couple through 0.1μF.
G
IN
1
12
Analog input. Green channel 1. DC couple or AC couple through 0.1μF.
B
IN
1
19
Analog input. Blue channel 1. DC couple or AC couple through 0.1μF.
RGB
GND
1
13
Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
1
14
Analog input. Sync on Green. Connect to G
IN
1 through a 0.01μF capacitor in series with a 500
Ω
resistor.
HSYNC
IN
1
33
Digital input, 5V tolerant, 240mV hysteresis, 1.2k
Ω
impedance to GND
A
. Connect to channel 1's HSYNC
signal through a 680
Ω
series resistor.
VSYNC
IN
1
44
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.
R
IN
2
22
Analog input. Red channel 2. DC couple or AC couple through 0.1μF.
G
IN
2
24
Analog input. Green channel 2. DC couple or AC couple through 0.1μF.
B
IN
2
28
Analog input. Blue channel 2. DC couple or AC couple through 0.1μF.
RGB
GND
2
25
Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
2
26
Analog input. Sync on Green. Connect to G
IN
1 through a 0.01μF capacitor in series with a 500
Ω
resistor.
HSYNC
IN
2
34
Digital input, 5V tolerant, 240mV hysteresis, 1.2k
Ω
impedance to GND
A
. Connect to channel 2's HSYNC
signal through a 680
Ω
series resistor.
VSYNC
IN
2
45
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.
CLOCKINV
IN
41
Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame
rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to
D
GND
if unused.
RESET
46
Digital input, 5V tolerant, active low, 70k
Ω
pull-up to V
D
. Take low for at least 1μs and then high again to
reset the X98024. This pin is not necessary for normal use and may be tied directly to the V
D
supply.
XTAL
IN
39
Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XTAL
OUT
40
Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XTALCLK
OUT
47
3.3V digital output. Buffered crystal clock output at f
XTAL
or f
XTAL
/2. May be used as system clock for other
system components.
SADDR
48
Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A
including R/W bit) when tied high.
SCL
50
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA
49
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
R
P
[7:0]
112-119
3.3V digital output. Red channel, primary pixel data. 58K pulldown when three-stated.
R
S
[7:0]
100-107
3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated.
G
P
[7:0]
90-97
3.3V digital output. Green channel, primary pixel data. 58K pulldown when three-stated.
G
S
[7:0]
80-87
3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated.
B
P
[7:0]
68-75
3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated.
B
S
[7:0]
55-62
3.3V digital output. Blue channel, secondary pixel data. 58K pulldown when three-stated.
DATACLK
121
3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 48
bit mode.
DATACLK
122
3.3V digital output. Inverse of DATACLK.
X98024
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PDF描述 |
|---|---|
| X98024L128-3.3 | 240MHz Triple Video Digitizer with Digital PLL |
| X98024L128-3.3-Z | 240MHz Triple Video Digitizer with Digital PLL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X98024_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:240MHz Triple Video Digitizer with Digital PLL |
| X98024L128-3.3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:240MHz Triple Video Digitizer with Digital PLL |
| X98024L128-3.3-Z | 功能描述:IC TRPL VID DIGITIZER 128MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| X98027 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:PRELIMINARY INFORMATION |
| X98027_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:275MHz Triple Video Digitizer with Digital PLL |
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