參數(shù)資料
型號: X98024
廠商: Intersil Corporation
英文描述: 240MHz Triple Video Digitizer with Digital PLL
中文描述: 240MHz的三路視頻數(shù)字化與數(shù)字鎖相環(huán)
文件頁數(shù): 6/29頁
文件大?。?/td> 295K
代理商: X98024
6
FN8220.0
June 6, 2005
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
D
0
R
P
/G
P
/B
P
[7:0]
HS
OUT
8.5 DATACLK Pipeline Latency
R
S
/G
S
/B
S
[7:0]
P
10
P
11
P
12
D
1
D
2
D
3
HSYNC
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 3. 24 BIT OUTPUT MODE
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
8.5 DATACLK Pipeline Latency
P
10
P
11
P
12
HSYNC
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
G
0
(Y
o
)
G
1
(Y
1
)
G
2
(Y
2
)
B
0
(U
o
)
R
1
(V
1
)
B
2
(U
2
)
G
P
[7:0]
R
P
[7:0]
B
P
[7:0]
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
X98024
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