FN8217.3 March 8, 2006 t HSYNCin-to-HSout = 7.5ns + (PHASE/64 +10.5)*tPIXEL
參數(shù)資料
型號(hào): X98014L128-3.3-Z
廠商: Intersil
文件頁(yè)數(shù): 27/29頁(yè)
文件大?。?/td> 0K
描述: IC VIDEO DIGITIZER TRPL 128MQFP
標(biāo)準(zhǔn)包裝: 66
類型: 視頻數(shù)字轉(zhuǎn)換器,3 通道 AFE
應(yīng)用: LCD 電視機(jī)/監(jiān)控器
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 1247 (CN2011-ZH PDF)
7
FN8217.3
March 8, 2006
t
HSYNCin-to-HSout = 7.5ns + (PHASE/64 +10.5)*tPIXEL
D
1
D
3
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
D
0
R
P/GP/BP[7:0]
HS
OUT
P
10
P
11
P
12
D
2
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
R
S/GS/BS[7:0]
HSYNC
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
HSYNC
FIGURE 5. 48 BIT OUTPUT MODE
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
P
10
P
11
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
HSYNC
IN
D
0
R
P/GP/BP[7:0]
D
2
D
1
R
S/GS/BS[7:0]
t
HSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
X98014
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