FN8217.3 March 8, 2006 HSOUT 125 3.3V digital output. HSYNC output aligned with pixel data. Use " />
參數(shù)資料
型號： X98014L128-3.3-Z
廠商： Intersil
文件頁數(shù)： 2/29頁
文件大?。?/td> 0K
描述： IC VIDEO DIGITIZER TRPL 128MQFP
標(biāo)準(zhǔn)包裝： 66
類型： 視頻數(shù)字轉(zhuǎn)換器，3 通道 AFE
應(yīng)用： LCD 電視機(jī)/監(jiān)控器
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1247 (CN2011-ZH PDF)
10
FN8217.3
March 8, 2006
HSOUT
125
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals)
VSOUT
126
3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after
the trailing edge of HSOUT. This signal is usually not needed - use VSYNCOUT as VSYNC source.
HSYNCOUT
127
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC
period. HSOUT should be used to detect the beginning of a line. This output will pass composite sync signals
and Macrovision signals if present on HSYNCIN or SOGIN.
VSYNCOUT
128
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a
frame and measure the VSYNC period.
VA
6, 11, 18, 20,
29, 35
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GNDA with 0.1F.
GNDA
3, 5, 8, 10, 15,
17, 21, 23, 27,
30, 36
Ground return for VA and VBYPASS.
VD
54, 67, 77, 89,
99, 111, 124
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GNDD with 0.1F.
GNDD
32, 43, 51, 53,
66, 76, 78, 88,
98, 108, 110,
120, 123
Ground return for VD, VCORE, VCOREADC, and VPLL.
VX
38
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GNDX with 0.1F.
GNDX
37
Ground return for VX.
VBYPASS
4, 9, 16
Bypass these pins to GNDA with 0.1F. Do not connect these pins to each other or anything else.
VREGIN
65
3.3V input voltage for VCORE voltage regulator. Connect to a 3.3V source, and bypass to GNDD with 0.1F.
VREGOUT
64
Regulated output voltage for VPLL, VCOREADC and VCORE; typically 1.9V. Connect only to VPLL,
VCOREADC and VCORE and bypass at input pins as instructed below. Do not connect to anything else - this
output can only supply power to VPLL, VCOREADC and VCORE.
VCOREADC
31
Internal power for the ADC’s digital logic. Connect to VREGOUT through a 10 resistor and bypass to GNDD
with 0.1F.
VPLL
42
Internal power for the PLL’s digital logic. Connect to VREGOUT through a 10 resistor and bypass to GNDD
with 0.1F.
VCORE
52, 79, 109
Internal power for core logic. Connect to VREGOUT and bypass each pin to GNDD with 0.1F.
NC
1, 2, 63
Reserved. Do not connect anything to these pins.
Pin Descriptions (Continued)
SYMBOL
PIN
DESCRIPTION
X98014
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