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參數(shù)資料
| 型號(hào)： | X98014L128-3.3-Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DIGITIZER TRPL 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器，3 通道 AFE |
| 應(yīng)用： | LCD 電視機(jī)/監(jiān)控器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1247 (CN2011-ZH PDF) |
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23
FN8217.3
March 8, 2006
Crystal Oscillator
An external 23MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
EMI Considerations
There are two possible sources of EMI on the X98014:
Crystal oscillator. The EMI from the crystal oscillator is
negligible. This is due to an amplitude-regulated, low
voltage sine wave oscillator circuit, instead of the typical
high-gain square wave inverter-type oscillator, so there
are no harmonics. The crystal oscillator is not a significant
source of EMI.
Digital output switching. This is the largest potential
source of EMI. However, the EMI is determined by the
PCB+ layout and the loading on the databus. The way to
control this is to put series resistors on the output of all the
digital pins. These resistor values should be adjusted to
optimize signal quality on the bus. Intersil recommends
starting with 22
and adjusting as necessary for the
particular PCB layout and device loading.
Recommendations for minimizing EMI are:
Minimize the databus trace length
Minimize the databus capacitive loading.
If EMI is a problem in the final design, increase the value of
the digital output series resistors to reduce slew rates on the
bus. This can only be done as long as the scaler’s setup and
hold timing requirements continue to be met.
Alternate Pixel Sampling
Two X98014s (AFEA and AFEB) may be used
simultaneously to achieve effective sample rates greater
than 140MHz. Each AFE is programmed with an HTOTAL
value equal to one-half of the total number of pixels in a line.
The CLOCKINVIN pin for AFEA is tied to ground, AFEB is
tied to VD. Both AFEs are otherwise programmed identically,
though some minor phase adjustment may be needed to
compensate for any propagation delay mismatch between
the two AFEs.
The CLOCKINVIN setting shifts the phase of AFEB by 180
degrees from AFEA. AFEA now samples the even pixels on
the rising edge of its DATACLK, while AFEB samples the odd
pixels on the rising edge of its clock. With each AFE in 24 bit
mode, two 24 bit data streams are generated (Figure 9).
With both AFEs configured for 48 bit mode, a 96 bit
datastream is generated (Figure 10).
In both cases, AFEA and AFEB are on different DATACLK
domains. In 24 bit mode, the data from each AFE must be
latched on the rising edge of that AFE’s DATACLK. In 48 bit
mode, the frequencies are low enough that the rising edge of
AFE B can be used to capture both AFEB and AFEA data.
HSYNC
IN
(to A and B)
DATACLK (A)
DATA (A)
HS
OUT (A)
DATACLK (B)
DATA (B)
HS
OUT (B)
DPLL Lock Edge
DATACLK Delay
CLKINV
IN (A) = GNDD
CLKINV
IN (B) = VD
D
0
D
2
D
3
D
N
D
1
D
N-3
D
N-1
D
N-2
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
P
10
P
11
P
12
P
N-3 PN-2
P
N-1
P
N
Analog Video In
(to A and B)
FIGURE 9. ALTERNATE PIXEL SAMPLING (24 BIT MODE)
X98014
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| X98017L128-3.3-Z | 功能描述:IC VIDEO DIGITIZER TRPL 128MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| X98021 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:210MHz Triple Video Digitizer with Digital PLL |
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