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參數(shù)資料
| 型號： | X95840WV20IZ-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digital Controlled Potentiometers |
| 中文描述： | QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 1145K |
| 代理商： | X95840WV20IZ-2.7 |
4
FN8213.1
September 27, 2005
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
I
CC1
V
CC
supply current
(Volatile write/read)
f
SCL
= 400kHz; SDA = Open; (for 2-Wire,
Active, Read and Volatile Write States only)
1
mA
I
CC2
V
CC
supply current
(nonvolatile write)
f
SCL
= 400kHz; SDA = Open; (for 2-Wire,
Active, Nonvolatile Write State only)
3
mA
I
SB
V
CC
current (standby)
V
CC
= +5.5V, 2 Wire Interface in Standby State
5
μA
V
CC
= +3.6V, 2 Wire Interface in Standby State
2
μA
I
LkgDig
Leakage current, at
pins A0, A1, A2, SDA, SCL,
and WP pins
Voltage at pin from GND to V
CC
-10
10
μA
t
DCP
(Note 15)
DCP wiper response time
SCL falling edge of last bit of DCP Data Byte to wiper
change
1
μs
Vpor
Power-on recall voltage
Minimum V
CC
at which memory recall occurs
1.8
2.6
V
VccRamp
V
CC
ramp rate
0.2
V/ms
t
D
(Note 15)
Power up delay
V
CC
above Vpor, to DCP Initial Value Register recall
completed, and 2-Wire Interface in standby state
3
ms
EEPROM SPECS
EEPROM Endurance
150,000
Cycles
EEPROM Retention
Temperature
≤
75°C
50
Years
SERIAL INTERFACE SPECS
V
IL
WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage
-0.3
0.3*Vcc
V
V
IH
WP, A2, A1, A0, SDA, and
SCL input buffer HIGH
voltage
0.7*Vcc
Vcc+0.3
V
Hysteresis
(Note 15)
SDA and SCL input buffer
hysteresis
0.05*
Vcc
V
V
OL
(Note 15) SDA output buffer LOW
voltage, sinking 4 mA
0
0.4
V
Cpin
(Note 15)
WP, A2, A1, A0, SDA, and
SCL pin capacitance
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
(Note 15)
Pulse width suppression time
at SDA and SCL inputs
Any pulse narrower than the max spec is suppressed.
50
ns
t
AA
(Note 15)
SCL falling edge to SDA
output data valid
SCL falling edge crossing 30% of V
CC
, until SDA exits
the 30% to 70% of V
CC
window.
900
ns
t
BUF
(Note 15)
Time the bus must be free
before the start of a new
transmission
SDA crossing 70% of V
CC
during a STOP condition, to
SDA crossing 70% of V
CC
during the following START
condition.
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing.
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing.
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge. Both crossing
70% of V
CC
.
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to SCL
falling edge crossing 70% of V
CC
.
600
ns
X95840
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