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參數(shù)資料
| 型號： | X9521 |
| 廠商： | Intersil Corporation |
| 英文描述： | Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules |
| 中文描述： | 光纖通道/千兆以太網(wǎng)控制半導(dǎo)體激光器光纖模塊 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 434K |
| 代理商： | X9521 |
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REV 1.1.9 1/30/03
Characteristics subject to change without notice.
4 of 26
www.xicor.com
X9521
– Preliminary Information
nate further data transmissions if an ACKNOWLEDGE is
not detected. The master must then issue a STOP condi-
tion to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9521
can be split up into three main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave Address
Byte being issued on the SDA pin. The Slave address
selects the part of the X9521 to be addressed, and speci-
fies if a Read or Write operation is to be performed.
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9521.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111
selects the DCP structures in the X9521. The CON-
STAT Register may be selected using the Internal
Device Address 010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
Data Output
from
Transmitter
Data Output
from
Receiver
8
1
9
Start
Acknowledge
Figure 3.
Acknowledge Response From Receiver
SCL
from
Master
SA6
SA7
SA5
SA3
SA2
SA1
SA0
DEVICE TYPE
IDENTIFIER
READ /
WRITE
SA4
Internal Address
(SA3 - SA1)
000
010
111
Internally Addressed
Device
EEPROM Array
CONSTAT Register
DCP
Bit SA0
Operation
0
WRITE
1
READ
R/W
Figure 4.
Slave Address Format
1
0
1
0
ADDRESS
INTERNAL
DEVICE
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| X9521_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual DCP, EEPROM Memory |
| X9521V20I | 功能描述:IC LASR CTRLR 2CHAN 5.5V 20TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
| X9521V20I-A | 功能描述:IC DCP DUAL EEPROM MEM 20-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
| X9521V20I-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual DCP, EEPROM Memory |
| X9521V20IZ-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual DCP, EEPROM Memory |
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