參數(shù)資料
型號(hào)： x9440
元件分類(lèi)： 數(shù)字電位計(jì)
英文描述： Dual Digitally-Controlled (EEPOT) Potentiometer & Voltage Comparator(雙數(shù)控電位器和電壓比較器)
中文描述： 雙數(shù)字控制（EEPOT）電位
文件頁(yè)數(shù)： 7/22頁(yè)
文件大小： 146K
代理商： X9440
X9440
Characteristics subject to change without notice.
7 of 22
REV 1.0 2/27/01
www.xicor.com
Figure 6. Three-Byte Command Sequence (Read)
Figure 7. Increment/Decrement Command Sequence
0
1
0
1
A1 A0
I3
I2
I1
I0
R1 R0 P1 P0
SCL
SI
CS
0
0
S0
0
0
D5 D4 D3 D2
D1 D0
Don’t Care
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
0
P1
P0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
Increment/Decrement
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse
(t
HIGH
) while SI is HIGH, the selected wiper will move
one resistor segment towards the V
H
terminal. Similarly,
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the V
L
terminal. A detailed illustration of the sequence and tim-
ing for this operation are shown in Figure 7 and 8.
Write in Process
The contents of the data registers are saved to nonvol-
atile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a write in process bit (WIP). The
WIP bit is read with a read status command.
Figure 8. Increment/Decrement Timing Limits
SCK
SI
V
W
INC/DEC CMD Issued
Voltage Out
t
WRID
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